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Chapter 8: Timing Diagrams 8–7
DDR and DDR2 High-Performance Controllers II
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
The following sequence corresponds with the numbered items in Figure 8–3:
1. The user logic requests the first read by asserting
local_read_req
signal, and the
size and address for this read. In this example, the request is a burst length of 2 to a
local address
0x000000
. This local address is mapped to the following memory
address in full-rate mode:
mem_row_address = 0×0000
mem_col_address = 0×0000<<2 = 0×0000
mem_bank_address = 0×00
2. The controller issues the first read memory command and address signals to the
ALTMEMPHY megafunction for it to send to the memory device.
3. The controller asserts the
afi_doing_rd
signal to indicate to the ALTMEMPHY
megafunction the number of clock cycles of read data it must expect for the first
read. The ALTMEMPHY megafunction uses the
afi_doing_rd
signal to enable its
capture registers for the expected duration of memory burst.
4. The ALTMEMPHY megafunction issues the first read command to the memory
and captures the read data from the memory.
5. The ALTMEMPHY megafunction returns the first data read to the controller after
resynchronizing the data to the
phy_clk
domain, by asserting the
afi_rdata_valid
signal when there is valid read data on the
afi_rdata
bus.
6. The controller returns the first read data to the user by asserting the
local_rdata_valid
signal when there is valid read data on the
local_rdata
bus. If
the ECC logic is disabled, there is no delay between the
afi_rdata
and the
local_rdata
buses. If there is ECC logic in the controller, there is one or three clock
cycles of delay between the
afi_rdata
and
local_rdata
buses.
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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