Altera Cyclone V GX FPGA Development Board Manual de usuario descargar pdf (Pagina 48)

2–40 Chapter 2: Board Components

Memory

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

DDR3B_CKE

L28 1.5-V SSTL Class I Column address select

DDR3B_CLK_P

P22 1.5-V SSTL Class I Differential output clock

DDR3B_CLK_N

P23 1.5-V SSTL Class I Differential output clock

DDR3B_CSN

U29 1.5-V SSTL Class I Chip select

DDR3B_DM2

H30 1.5-V SSTL Class I Write mask byte lane

DDR3B_DM3

L30 1.5-V SSTL Class I Write mask byte lane

DDR3B_DQ16

J29 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ17

G26 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ18

J27 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ19

H29 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ20

J28 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ21

F30 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ22

K27 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ23

F26 1.5-V SSTL Class I Data bus byte lane 2

DDR3B_DQ24

J30 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ25

K25 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ26

G27 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ27

L25 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ28

L29 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ29

N27 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ30

K26 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQ31

L26 1.5-V SSTL Class I Data bus byte lane 3

DDR3B_DQS_P2

N22

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 2

DDR3B_DQS_N2

M23

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 2

DDR3B_DQS_P3

N24

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 3

DDR3B_DQS_N3

N25

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 3

DDR3B_ODT

V29 1.5-V SSTL Class I On-die termination enable

DDR3B_RASN

T29 1.5-V SSTL Class I Row address select

DDR3B_RESETN

AB27 1.5-V SSTL Class I Reset

DDR3B_WEN

T28 1.5-V SSTL Class I Write enable

DDR3B_ZQ2

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x8 (U19)

DDR3B_A0

Y30 1.5-V SSTL Class I Address bus

DDR3B_A1

R28 1.5-V SSTL Class I Address bus

DDR3B_A2

AA29 1.5-V SSTL Class I Address bus

Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board Reference

Schematic

Signal Name

Cyclone V GX

Pin Number

I/O Standard Description

1 2 ... 43 44 45 46 47 48 49 50 51 52 53 ... 59 60

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