Altera Cyclone V GT FPGA Development Board Manual de usuario descargar pdf (Pagina 55)

Chapter 2: Board Components 2–47

Memory

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

DDR3B_CKE

AF32 1.5-V SSTL Class I Column address select

DDR3B_CLK_P

R30

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3B_CLK_N

R29

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3B_CSN

V27 1.5-V SSTL Class I Chip select

DDR3B_DM6

L31 1.5-V SSTL Class I Write mask byte lane

DDR3B_DM7

H28 1.5-V SSTL Class I Write mask byte lane

DDR3B_DQ48

N28 1.5-V SSTL Class I Data bus byte lane 6

DDR3B_DQ49

L30 1.5-V SSTL Class I Data bus byte lane 6

DDR3B_DQ50

P30 1.5-V SSTL Class I Data bus byte lane 6

DDR3B_DQ51

K30 1.5-V SSTL Class I Data bus byte lane 6

DDR3B_DQ52

J32 1.5-V SSTL Class I Data bus byte lane 6

DDR3B_DQ53

H32 1.5-V SSTL Class I Data bus byte lane 6

DDR3B_DQ54

M31 1.5-V SSTL Class I Data bus byte lane 6

DDR3B_DQ55

H31 1.5-V SSTL Class I Data bus byte lane 6

DDR3B_DQ56

G30 1.5-V SSTL Class I Data bus byte lane 7

DDR3B_DQ57

K29 1.5-V SSTL Class I Data bus byte lane 7

DDR3B_DQ58

G31 1.5-V SSTL Class I Data bus byte lane 7

DDR3B_DQ59

M30 1.5-V SSTL Class I Data bus byte lane 7

DDR3B_DQ60

J30 1.5-V SSTL Class I Data bus byte lane 7

DDR3B_DQ61

M29 1.5-V SSTL Class I Data bus byte lane 7

DDR3B_DQ62

J29 1.5-V SSTL Class I Data bus byte lane 7

DDR3B_DQ63

L28 1.5-V SSTL Class I Data bus byte lane 7

DDR3B_DQS_P6

R23

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 6

DDR3B_DQS_N6

R24

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 6

DDR3B_DQS_P7

P24

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 7

DDR3B_DQS_N7

P25

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 7

DDR3B_ODT

AA32 1.5-V SSTL Class I On-die termination enable

DDR3B_RASN

Y32 1.5-V SSTL Class I Row address select

DDR3B_RESETN

AG31 1.5-V SSTL Class I Reset

DDR3B_WEN

AM34 1.5-V SSTL Class I Write enable

DDR3B_ZQ03

— 1.5-V SSTL Class I ZQ impedance calibration

Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 6)

Board Reference

Schematic

Signal Name

Cyclone V GT

Pin Number

I/O Standard Description

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 65 66

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