Altera Cyclone V GT FPGA Development Board Manual de usuario descargar pdf (Pagina 27)

Chapter 2: Board Components 2–19

Clock Circuitry

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

Figure 2–5 shows the default frequencies of all external clocks going to the

Cyclone V GT FPGA on the development board.

Table 2–11 lists the oscillators, its I/O standard, and voltages required for the

development board.

Figure 2–5. Cyclone V GT FPGA Development Board Clocks

Reference

Clock Input

SMA

50 MHz

Si570

100 MHz

Default

QL2

QL1

QL0

U13

Output

SMA

CLK10

CLKINTOP_P/N

CLK5

CLK_125M_P/N

CLK6

CLKINA_50

CLK7

CLKIN_R_P/N

50 MHz

REFCLK_QL3_P/N

(HSMB)

REFCLK_QL1_P/N

(PCIe)

PCIE_REFCLK_P/N

CLK2

CLKINBOT_P/N

Buffer

100 MHz

Default

SMA

125 M

Buffer

50 MHz

CLKIN_MAX_50

Si571

148.5 MHz

Default

SDI

(148.5 M, 148.35 M)

REFCLK_QL2_P/N

(SDI, HSMA)

U52

Table 2–11. On-Board Oscillators (Part 1 of 2)

Source

Schematic Signal

Name

Frequency I/O Standard

Cyclone V GT

Pin Number

Application

CLKIN_50

50.000 MHz 1.5-V CMOS

V28

FPGA bank 5B (CLK6p) for

general purpose logic

CLKIN_MAX_50

—

FPGA bank 5B (CLK6p) for

general purpose logic in the

MAX V CPLD

CLK_125M_P

125.000 MHz LVDS

U31 FPGA bank 6A (CLK5p)

CLK_125M_N

U30 FPGA bank 6A (CLK5n)

1 2 ... 22 23 24 25 26 27 28 29 30 31 32 ... 65 66

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