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CPU Interface Signals
Table 3-12: CPRI v6.0 IP Core CPU Interface Signals
The CPRI v6.0 IP core CPU interface has the following features:
• Avalon-MM slave interface compliant.
• Provides support for single cycle read and write operations: you can read or write a single register in a single
access operation.
• Supports a single cpu_clk clock cycle read latency and a zero cpu_clk clock cycle write latency for most
registers.
Signal Name Direction Description
cpu_clk Input Clocks the signals on the CPRI v6.0 CPU interface. Supports
any frequency that the device fabric supports.
cpu_reset Input Active low reset signal. Resets the CPRI v6.0 CPU interface
and all of the registers to which it provides access.
You should hold this signal asserted for one full cpu_clk
cycle to ensure it is captured by the IP core.
cpu_address[15:0]
Input Address for reads and writes. All CPRI v6.0 control and
status registers are 32 bits wide. Therefore, this address is a
word address (addresses a 4-byte (32-bit) word), not a byte
address.
cpu_byteenable[3:0] Input Data-byte enable signal
cpu_read
Input You must assert this signal to request a read transfer
cpu_write
Input You must assert this signal to request a write transfer
cpu_writedata[31:0]
Input Write data
cpu_readdata[31:0]
Output Read data
cpu_waitrequest
Output Indicates that the control and status interface is busy
executing an operation. When the IP core deasserts this
signal, the operation is complete and the read data is valid.
cpu_irq
Output Interrupt request. All interrupts that you enable in the
relevant register fields, assert this interrupt signal when they
are triggered. You must check the relevant register fields to
determine the cause or causes of the interrupt assertion.
Related Information
Avalon Interface Specifications
For more information about the Avalon-MM protocol, including timing diagrams, refer to the Avalon
Memory-Mapped Interfaces chapter.
3-36
CPU Interface Signals
UG-01156
2014.08.18
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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