Altera CPRI v6.0 MegaCore Function Manual de usuario Pagina 64

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MII Status Signals
Signal Name Direction Description
mii_tx_fifo_status[3:0] Output Ethernet Tx PCS FIFO fill level status. The individual bits
have the following meanings:
Bit [3]: Empty
Bit [2]: Almost empty
Bit [1]: Full
Bit [0]: Almost full
mii_rx_fifo_status[3:0] Output Ethernet Rx PCS FIFO fill level status. The individual bits
have the following meanings:
Bit [3]: Empty
Bit [2]: Almost empty
Bit [1]: Full
Bit [0]: Almost full
Figure 3-25: RX MII Timing Diagram
mii_rxclk
mii_rxdv
mii_rxd
mii_rxer
D1 D2 /F/ D4 D5 D6 D7 XX
Error Received
Discard Part
of Payload
4’b0101
3-34
Media Independent Interface (MII) to External Ethernet Block
UG-01156
2014.08.18
Altera Corporation
Functional Description
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