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You must connect the external reset controller signals and the CPRI v6.0 IP core reset controller interface
signals according to the following rules. Refer to Integrating Your IP Core in Your Design: Required
External Blocks on page 2-11 for an illustration of the connections.
• Connect the tx_digitalreset, tx_analogreset, tx_ready, rx_digitalreset, rx_analogreset,
and rx_ready output signals of the reset controllers to the xcvr_tx_digitalreset,
xcvr_tx_analogreset, xcvr_tx_ready, xcvr_rx_digitalreset, xcvr_rx_analogreset, and
xcvr_rx_readyinput signals of the CPRI v6.0 IPcore, respectively.
• Connect the xcvr_rx_is_lockedtodata output pin of the CPRI v6.0 IP core to the rx_is_lockedto-
data input signal of the RX reset controller.
User logic must provide the connections. Refer to the demonstration testbench for example working user
logic including one correct method to instantiate and connect the external reset controllers.
Related Information
• Interface to the External Reset Controller on page 3-47
• Integrating Your IP Core in Your Design: Required External Blocks on page 2-11
Figure illustrates the required connections.
• Altera Transceiver PHY IP Core User Guide
Information about how to configure the Altera Transceiver PHY Reset Controller for your Arria V GZ
or Stratix V design.
• Arria 10 Transceiver PHY User Guide
Information about how to configure the Altera Transceiver PHY Reset Controller for your Arria 10
design.
Adding the Transceiver Reconfiguration Controller
CPRI v6.0 IP cores that target Arria V GZ and Stratix V devices require an external reconfiguration
controller to compile and to function correctly in hardware. CPRI v6.0 IP cores that target Arria 10
devices include a transceiver reconfiguration controller block and do not require an external reconfigura‐
tion controller.
You can use the IP Catalog to generate the Altera Transceiver Reconfiguration Controller IP core.
When you configure the Altera Transceiver Reconfiguration Controller, you must specify the number of
reconfiguration interfaces. The number of reconfiguration interfaces required for the CPRI v6.0 IP core is
two . You can configure your reconfiguration controller with additional interfaces if your design connects
with multiple transceiver IP cores. You can leave other options at the default settings or modify them for
your preference.
You should connect the reconfig_to_xcvr and reconfig_from_xcvr ports of the CPRI v6.0 IP core to
the corresponding ports of the reconfiguration controller.
You must drive the CPRI v6.0 IP core reconfig_clk input port and the Altera Transceiver Reconfigura‐
tion Controller mgmt_clk_clk input port from the same clock source. Drive both ports at a clock
frequency in the range of 100–150MHz.
Related Information
• Arria V GZ and Stratix V Transceiver Reconfiguration Interface on page 3-46
• Altera Transceiver PHY IP Core User Guide
For more information about the Altera Transceiver Reconfiguration Controller.
UG-01156
2014.08.18
Adding the Transceiver Reconfiguration Controller
2-15
Getting Started with the CPRI v6.0 IP Core
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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