Altera Arria V GX FPGA Development Board Manual de usuario Pagina 67
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Chapter 2: Board Components 2–57
Components and Interfaces
November 2013 Altera Corporation Arria V GX FPGA Development Board
Reference Manual
Bull's Eye Connector
The development board comes with Samtec's Bull's Eye system, which includes four
SMA cables along with the insertion tool to insert the cables into the connector.
The Bull's Eye high-density RF interconnect system allows many channels to be
compacted into a small area on a printed circuit board at a comparable performance to
SMA connectors. The cables allow you to monitor only two differential signals at a
time. You can move the cables from one channel to another using the tool included
with this board.
1 You can order more cables from www.samtec.com and these cable systems can be
reused on other boards.
f For specific instructions on how to install the connector to the board and insert the
cables into the connector, refer to Samtec's web page regarding this system.
Table 2–54 lists the Bull’s eye connector pin assignments, signal names, and functions.
Table 2–52. Bull’s Eye Connector Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J16)
Schematic Signal Name
Arria V GX FPGA
Pin Number
I/O Standard Description
4
BULLSEYE_SMA_CLKN
— LVDS or 2.5-V Clock buffer
3
BULLSEYE_SMA_CLKP
— LVDS or 2.5-V Clock buffer
21
SMA_A_10G_RX_N0
G2 LVDS or 2.5-V Transceiver channel
2
SMA_A_10G_RX_N1
H38 LVDS or 2.5-V Transceiver channel
22
SMA_A_10G_RX_P0
G1 LVDS or 2.5-V Transceiver channel
1
SMA_A_10G_RX_P1
H39 LVDS or 2.5-V Transceiver channel
7
SMA_A_6G_RX_N2
C2 LVDS or 2.5-V Transceiver channel
11
SMA_A_6G_RX_P2
C1 LVDS or 2.5-V Transceiver channel
13
SMA_A_TX_L15_N
G36 LVDS or 2.5-V Transceiver channel
12
SMA_A_TX_L15_P
G37 LVDS or 2.5-V Transceiver channel
17
SMA_A_TX_R16_N
F4 LVDS or 2.5-V Transceiver channel
18
SMA_A_TX_R16_P
F3 LVDS or 2.5-V Transceiver channel
8
SMA_A_TX_R17_N
B4 LVDS or 2.5-V Transceiver channel
9
SMA_A_TX_R17_P
B3 LVDS or 2.5-V Transceiver channel
15
SMA_B_10G_RX_N1
H38 LVDS or 2.5-V Transceiver channel
16
SMA_B_10G_RX_P1
H39 LVDS or 2.5-V Transceiver channel
5
SMA_B_6G_RX_N0
AC2 LVDS or 2.5-V Transceiver channel
6
SMA_B_6G_RX_P0
AC1 LVDS or 2.5-V Transceiver channel
19
SMA_B_TX_L15_N
G36 LVDS or 2.5-V Transceiver channel
20
SMA_B_TX_L15_P
G37 LVDS or 2.5-V Transceiver channel
10
SMA_B_TX_R6_N
AB4 LVDS or 2.5-V Transceiver channel
14
SMA_B_TX_R6_P
AB3 LVDS or 2.5-V Transceiver channel
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Dual FPGA 7
- 1–4 Chapter 1: Overview 8
- 1–6 Chapter 1: Overview 10
- Handling the Board 10
- 2. Board Components 11
- Board Overview 12
- I/O Resources 17
- II CPLD EPM2210 System 20
- II device (U2) 20
- Table 2–7 lists the MAX 24
- Configuration 25
- Figure 2–4. JTAG Chain 26
- Figure 2–5. PFL Configuration 28
- Status Elements 29
- Setup Elements 31
- JTAG Settings DIP Switch 32
- CPU Reset Push Button 33
- MAX II Reset Push Button 33
- Clock Circuitry 34
- FPGA development board 35
- Off-Board Clock Input/Output 37
- General User Input/Output 39
- User-Defined DIP Switches 40
- User-Defined LEDs 41
- HSMC User-Defined LEDs 42
- SDI Video Output/Input 44
- Components and Interfaces 47
- 10/100/1000 Ethernet 50
- SFP+ Module 59
- FMC Connector 60
- Bull's Eye Connector 67
- DDR3A for FPGA 1 68
- I/O setting and direction 69
- DDR3B/C for FPGA 2 73
- Power Supply 83
- Power Measurement 85
- Notes to Table 2–64: 87
- Info–2 Additional Information 90
- Typographic Conventions 90
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