Altera Arria V GT FPGA Development Board Manual de usuario descargar pdf (Pagina 49)

Chapter 2: Board Components 2–39

Components and Interfaces

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

HSMA_RX_N7

E2 1.5-V PCML Transceiver RX bit 7n

HSMA_TX_P6

H3 1.5-V PCML Transceiver TX bit 6

HSMA_RX_P6

J1 1.5-V PCML Transceiver RX bit 6

HSMA_TX_N6

H4 1.5-V PCML Transceiver TX bit 6n

HSMA_RX_N6

J2 1.5-V PCML Transceiver RX bit 6n

HSMA_TX_P5

K3 1.5-V PCML Transceiver TX bit 5

HSMA_RX_P5

L1 1.5-V PCML Transceiver RX bit 5

HSMA_TX_N5

K4 1.5-V PCML Transceiver TX bit 5n

HSMA_RX_N5

L2 1.5-V PCML Transceiver RX bit 5n

HSMA_TX_P4

M3 1.5-V PCML Transceiver TX bit 4

HSMA_RX_P4

N1 1.5-V PCML Transceiver RX bit 4

HSMA_TX_N4

M4 1.5-V PCML Transceiver TX bit 4n

HSMA_RX_N4

N2 1.5-V PCML Transceiver RX bit 4n

HSMA_TX_P3

AH3 1.5-V PCML Transceiver TX bit 3

HSMA_RX_P3

AJ1 1.5-V PCML Transceiver RX bit 3

HSMA_TX_N3

AH4 1.5-V PCML Transceiver TX bit 3n

HSMA_RX_N3

AJ2 1.5-V PCML Transceiver RX bit 3n

HSMA_TX_P2

V3 1.5-V PCML Transceiver TX bit 2

HSMA_RX_P2

W1 1.5-V PCML Transceiver RX bit 2

HSMA_TX_N2

V4 1.5-V PCML Transceiver TX bit 2n

HSMA_RX_N2

W2 1.5-V PCML Transceiver RX bit 2n

HSMA_TX_P1

T3 1.5-V PCML Transceiver TX bit 1

HSMA_RX_P1

U1 1.5-V PCML Transceiver RX bit 1

HSMA_TX_N1

T4 1.5-V PCML Transceiver TX bit 1n

HSMA_RX_N1

U2 1.5-V PCML Transceiver RX bit 1n

HSMA_TX_P0

P3 1.5-V PCML Transceiver TX bit 0

HSMA_RX_P0

R1 1.5-V PCML Transceiver RX bit 0

HSMA_TX_N0

P4 1.5-V PCML Transceiver TX bit 0n

HSMA_RX_N0

R2 1.5-V PCML Transceiver RX bit 0n

HSMA_SDA

AT14 2.5-V CMOS Management serial data

HSMA_SCL

AU15 2.5-V CMOS Management serial clock

JTAG_TCK

AV34 2.5-V CMOS JTAG clock signal

HSMA_JTAG_TMS

— 2.5-V CMOS JTAG mode select signal

HSMA_JTAG_TDO

— 2.5-V CMOS JTAG data output

AVB_JTAG_TDO

AT34 2.5-V CMOS JTAG data output

HSMA_CLK_OUT0

AL14 LVDS or 2.5-V Dedicated CMOS clock out

HSMA_CLK_IN0

AT7 LVDS or 2.5-V Dedicated CMOS clock in

HSMA_D0

AG16 2.5-V CMOS Dedicated CMOS I/O bit 0

Table 2–26. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)

Board

Reference (J1)

Schematic Signal Name

Arria V GT

FPGA

Pin Number

I/O Standard Description

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 85 86

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Altera Arria V GT FPGA Development Board Manual de usuario Pagina 49

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