Altera Arria V Avalon-MM Manual de usuario Pagina 163
- Pagina / 166
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Date Version Changes Made
• Added definition of nreset_status for variants using the
Avalon-MM interface.
• In Transaction Layer Routing Rules and Programming Model for
Avalon-MM Root Port , added the fact that Type 0 Configuration
Requests sent to the Root Port are not filtered by the device
number. Application Layer software must filter out requests for
device number greater than 0.
• Added Recommended Reset Sequence to Avoid Link Training Issues
to the Debugging chapter.
• Added limitation for RxmIrq_<n>_i[<m>:0] when interrupts are
received on consecutive cycles.
• Updated timing diagram for tl_cfg_ctl.
• Removed I/O Read Request and I/O Write Requests from TLPs
supported for Avalon-MM interface.
• Added note that the LTSSM interface can be used for SignalTap
debugging.
• Added restriction on the use of dynamic transceiver reconfigura‐
tion when CvP is enabled.
2014.05.06
13.0
Made the following changes:
• Timing models are now final.
• Added instructions for running the Single Dword variant.
• Corrected definition of test_in[4:1]. This vector must be set to
4’b0100.
• Corrected connection for mgmt_clk_clk in Figure 3-2.
• Corrected definition of nPERSTL*. The device has 1 nPERSTL* pin
for each instance of the Hard IP for PCI Express in the device.
• Corrected feature comparison table in Datasheet chapter. The
Avalon-MM Hard IP for PCI Express IP Core does not support
legacy endpoints.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the following table.
Contact
(1)
Contact Method Address
Technical support Website www.altera.com/support
Technical training
Website www.altera.com/training
Email [email protected]
C-4
How to Contact Altera
UG-01105_avmm
2014.08.18
Altera Corporation
Additional Information
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Release Information 6
- Device Family Support 6
- Altera FPGA 7
- IP Core Verification 9
- Debug Features 9
- Recommended Speed Grades 10
- Hard IP for PCI Express 12
- Running Qsys 13
- Generating the Example Design 14
- Programming a Device 18
- Quartus II Programmer 19
- Parameter Settings 20
- Parameter Value Description 21
- Device Capabilities 23
- Error Reporting 24
- Link Capabilities 25
- MSI and MSI-X Capabilities 25
- Power Management 27
- Subscribe 31
- RX Avalon-MM Master Signals 33
- Clock Signals 38
- Reset Signals 38
- Signal Direction Description 39
- Hard IP Status 40
- IntxReq_i 44
- IntAck_o 44
- Hard IP Status Extension 46
- Field and Bit Map 54
- 0134678951 54
- Serial Interface Signals 55
- 9 Ch 18 Ch 56
- Variant Data CMU Clock 57
- PIPE Interface Signals 58
- Test Signals 62
- Registers 63
- Altera-Defined VSEC Registers 71
- CvP Registers 72
- Address Range Register 76
- Bit Name Access Description 77
- Bits Name Access Description 78
- PCI Express Mailbox Registers 79
- Avalon-MM Mailbox Registers 83
- Address Name Access 84
- Description 84
- Byte Offset 84
- Register Dir Description 84
- Sending a Write TLP 90
- Root Port TLP Data Registers 92
- Bits Register Description 95
- Reset and Clocks 98
- Example Design 99
- UG-01105_avmm 100
- 2014.12.15 100
- Clock Domains 102
- Data Rate Frequency 103
- Related Information 103
- Clock Summary 104
- Interrupts for Endpoints 105
- MSI/MSI‑X Support 107
- Qsys System 108
- Error Handling 109
- Physical Layer Errors 110
- Data Link Layer Errors 110
- Transaction Layer Errors 111
- Error Type Description 112
- Status Bit Conditions 115
- IP Core Architecture 117
- Hard IP for PCI Express 118
- Clocks and Reset 119
- Transceiver Reconfiguration 119
- Interrupts 119
- Data Link Layer 120
- Altera Corporation 121
- Send Feedback 121
- Physical Layer 122
- TX Packets 123
- Avalon‑MM Bridge TLPs 127
- Byte Enable Value Description 128
- PCI Express Avalon-MM Bridge 130
- RX Block 136
- Avalon-MM RX Master Block 136
- TX Block 137
- Interrupt Handler Block 137
- Design Implementation 139
- Making Pin Assignments 140
- Optional Features 141
- ECRC on the RX Path 142
- ECRC on the TX Path 143
- Enable PLL calibration 145
- Debugging 148
- Setting Up Simulation 149
- Use Third-Party PCIe Analyzer 150
- BIOS Enumeration Issues 151
- Address[31:2] 152
- Figure A-6: I/O Read Request 154
- 7 6 5 4 3 2 1 0 158
- Core Config 8 4 1 158
- Additional Information 160
- Date Version Changes Made 161
- How to Contact Altera 163
- Typographic Conventions 164
- Visual Cue Meaning 165
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