Altera Arria V Avalon-MM Manual de usuario Pagina 135
- Pagina / 166
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Figure 9-10: Avalon-MM-to-PCI Express Address Translation
The following figure depicts the Avalon-MM-to-PCI Express address translation process. In this figure
the variables represent the following paramers:
• N—the number of pass-through bits.
• M—the number of Avalon-MM address bits.
• P—the number of PCIe address bits.
• Q—the number of translation table entries.
• Sp[1:0]—the space indication for each entry.
PCIe Address Q-1
SpQ-1
Space Indication
PCI Express address from Table Entry
becomes High PCI Express address bits
PCI Express Address
High
Low
P-1 N N-1 0
Low address bits unchanged
Avalon-MM-to-PCI Express
Address Translation Table
(Q entries by P-N bits wide)
PCIe Address 0 Sp0
PCIe Address 1 Sp1
Avalon-MM Address
High
Slave Base
Address
Low
M-131 M N N-1 0
Table updates from
control register port
High Avalon-MM Address
Bits Index table
Completer Only Single Dword Endpoint
The completer only single dword endpoint is intended for applications that use the PCI Express protocol
to perform simple read and write register accesses from a host CPU. The completer only single dword
endpoint is a hard IP implementation available for Qsys systems, and includes an Avalon-MM interface to
the Application Layer. The Avalon-MM interface connection in this variation is 32 bits wide. This
endpoint is not pipelined; at any time a single request can be outstanding.
The completer-only single dword endpoint supports the following requests:
• Read and write requests of a single dword (32 bits) from the Root Complex
• Completion with Completer Abort status generation for other types of non-posted requests
• INTX or MSI support with one Avalon-MM interrupt source
UG-01105_avmm
2014.12.15
Completer Only Single Dword Endpoint
9-19
IP Core Architecture
Altera Corporation
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Release Information 6
- Device Family Support 6
- Altera FPGA 7
- IP Core Verification 9
- Debug Features 9
- Recommended Speed Grades 10
- Hard IP for PCI Express 12
- Running Qsys 13
- Generating the Example Design 14
- Programming a Device 18
- Quartus II Programmer 19
- Parameter Settings 20
- Parameter Value Description 21
- Device Capabilities 23
- Error Reporting 24
- Link Capabilities 25
- MSI and MSI-X Capabilities 25
- Power Management 27
- Subscribe 31
- RX Avalon-MM Master Signals 33
- Clock Signals 38
- Reset Signals 38
- Signal Direction Description 39
- Hard IP Status 40
- IntxReq_i 44
- IntAck_o 44
- Hard IP Status Extension 46
- Field and Bit Map 54
- 0134678951 54
- Serial Interface Signals 55
- 9 Ch 18 Ch 56
- Variant Data CMU Clock 57
- PIPE Interface Signals 58
- Test Signals 62
- Registers 63
- Altera-Defined VSEC Registers 71
- CvP Registers 72
- Address Range Register 76
- Bit Name Access Description 77
- Bits Name Access Description 78
- PCI Express Mailbox Registers 79
- Avalon-MM Mailbox Registers 83
- Address Name Access 84
- Description 84
- Byte Offset 84
- Register Dir Description 84
- Sending a Write TLP 90
- Root Port TLP Data Registers 92
- Bits Register Description 95
- Reset and Clocks 98
- Example Design 99
- UG-01105_avmm 100
- 2014.12.15 100
- Clock Domains 102
- Data Rate Frequency 103
- Related Information 103
- Clock Summary 104
- Interrupts for Endpoints 105
- MSI/MSI‑X Support 107
- Qsys System 108
- Error Handling 109
- Physical Layer Errors 110
- Data Link Layer Errors 110
- Transaction Layer Errors 111
- Error Type Description 112
- Status Bit Conditions 115
- IP Core Architecture 117
- Hard IP for PCI Express 118
- Clocks and Reset 119
- Transceiver Reconfiguration 119
- Interrupts 119
- Data Link Layer 120
- Altera Corporation 121
- Send Feedback 121
- Physical Layer 122
- TX Packets 123
- Avalon‑MM Bridge TLPs 127
- Byte Enable Value Description 128
- PCI Express Avalon-MM Bridge 130
- RX Block 136
- Avalon-MM RX Master Block 136
- TX Block 137
- Interrupt Handler Block 137
- Design Implementation 139
- Making Pin Assignments 140
- Optional Features 141
- ECRC on the RX Path 142
- ECRC on the TX Path 143
- Enable PLL calibration 145
- Debugging 148
- Setting Up Simulation 149
- Use Third-Party PCIe Analyzer 150
- BIOS Enumeration Issues 151
- Address[31:2] 152
- Figure A-6: I/O Read Request 154
- 7 6 5 4 3 2 1 0 158
- Core Config 8 4 1 158
- Additional Information 160
- Date Version Changes Made 161
- How to Contact Altera 163
- Typographic Conventions 164
- Visual Cue Meaning 165
Relacionado con productos y manuales para Instrumentos de medición Altera Arria V Avalon-MM
Instrumentos de medición Altera DDR3 SDRAM High-Performance Controller and ALTMEMP Manual de usuario
(10 paginas)
(10 paginas)
Instrumentos de medición Altera DDR SDRAM High-Performance Controllers and ALTMEMP Manual de usuario
(140 paginas)
(140 paginas)
Instrumentos de medición Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manual de usuario
(3 paginas)
(3 paginas)
© 2020, manymanuals.es. Todos los derechos reservados | 0.047 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales