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packets can be transmitted. If you encounter link training issues, viewing the actual data in hardware
should help you determine the root cause. You can use the following tools to provide hardware visibility:
• SignalTap II Embedded Logic Analyzer
• Third-party PCIe analyzer
You can use SignalTap II Embedded Logic Analyzer to diagnose the LTSSM state transitions that are
occurring on the PIPE interface. The ltssmstate[4:0] bus encodes the status of LTSSM. The LTSSM
state machine reflects the Physical Layer’s progress through the link training process. For a complete
description of the states these signals encode, refer to Status, Link Training and Reset Signals. When link
training completes successfully and the link is up, the LTSSM should remain stable in the L0 state. When
link issues occur, you can monitor ltssmstate[4:0] to determine the cause.
Related Information
Reset
Setting Up Simulation
Changing the simulation parameters reduces simulation time and provides greater visibility.
Changing Between Serial and PIPE Simulation
By default, the Altera testbench runs a serial simulation. You can change between serial and PIPE
simulation by editing the top-level testbench file.
The hip_ctrl_simu_mode_pipe signal and enable_pipe32_sim_hwtcl parameter, specify serial or PIPE
simulation. When both are set to 1'b0, the simulation runs in serial mode. When both are set to 1'b1, the
simulation runs in PIPE mode. Complete the following steps to enable PIPE simulation. These steps
assume that the actual testbench in Gen1 x4 with an Avalon-MM 64-bit interface.
1. In the top-level testbench, which is <working_dir>/<variant>/testbench/<variant>_tb/simulation/<variant>_
tb.v, change the signal, hip_ctrl_simu_mode_pipe to 1'b1 as shown:
pcie_de_gen1_x4_ast64 pcie_de_gen1_x4_ast64_x_inst (.dut_hip_ctrl_simu_mode_pipe
( 1'b1 ),
2. In the top-level HDL module for the Hard IP which is <working_dir>/<variant>/testbench/<variant>_tb/
simulation/submodules/<variant>.v change the parameter enable_pipe32_sim_hwtcl parameter to 1'b1
as shown:
altpcie_<dev>_hip_ast_hwtcl #( .enable_pipe32_sim_hwtcl ( 1 ),
Using the PIPE Interface for Gen1 and Gen2 Variants
Running the simulation in PIPE mode reduces simulation time and provides greater visibility.
Complete the following steps to simulate using the PIPE interface:
1. Change to your simulation directory, <work_dir>/<variant>/testbench/<variant>_tb/simulation
2. Open <variant>_tb.v.
3. Search for the string, serial_sim_hwtcl. Set the value of this parameter to 0 if it is 1.
4. Save <variant>_tb.v.
13-2
Setting Up Simulation
UG-01105_avmm
2014.12.15
Altera Corporation
Debugging
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Release Information 6
- Device Family Support 6
- Altera FPGA 7
- IP Core Verification 9
- Debug Features 9
- Recommended Speed Grades 10
- Hard IP for PCI Express 12
- Running Qsys 13
- Generating the Example Design 14
- Programming a Device 18
- Quartus II Programmer 19
- Parameter Settings 20
- Parameter Value Description 21
- Device Capabilities 23
- Error Reporting 24
- Link Capabilities 25
- MSI and MSI-X Capabilities 25
- Power Management 27
- Subscribe 31
- RX Avalon-MM Master Signals 33
- Clock Signals 38
- Reset Signals 38
- Signal Direction Description 39
- Hard IP Status 40
- IntxReq_i 44
- IntAck_o 44
- Hard IP Status Extension 46
- Field and Bit Map 54
- 0134678951 54
- Serial Interface Signals 55
- 9 Ch 18 Ch 56
- Variant Data CMU Clock 57
- PIPE Interface Signals 58
- Test Signals 62
- Registers 63
- Altera-Defined VSEC Registers 71
- CvP Registers 72
- Address Range Register 76
- Bit Name Access Description 77
- Bits Name Access Description 78
- PCI Express Mailbox Registers 79
- Avalon-MM Mailbox Registers 83
- Address Name Access 84
- Description 84
- Byte Offset 84
- Register Dir Description 84
- Sending a Write TLP 90
- Root Port TLP Data Registers 92
- Bits Register Description 95
- Reset and Clocks 98
- Example Design 99
- UG-01105_avmm 100
- 2014.12.15 100
- Clock Domains 102
- Data Rate Frequency 103
- Related Information 103
- Clock Summary 104
- Interrupts for Endpoints 105
- MSI/MSI‑X Support 107
- Qsys System 108
- Error Handling 109
- Physical Layer Errors 110
- Data Link Layer Errors 110
- Transaction Layer Errors 111
- Error Type Description 112
- Status Bit Conditions 115
- IP Core Architecture 117
- Hard IP for PCI Express 118
- Clocks and Reset 119
- Transceiver Reconfiguration 119
- Interrupts 119
- Data Link Layer 120
- Altera Corporation 121
- Send Feedback 121
- Physical Layer 122
- TX Packets 123
- Avalon‑MM Bridge TLPs 127
- Byte Enable Value Description 128
- PCI Express Avalon-MM Bridge 130
- RX Block 136
- Avalon-MM RX Master Block 136
- TX Block 137
- Interrupt Handler Block 137
- Design Implementation 139
- Making Pin Assignments 140
- Optional Features 141
- ECRC on the RX Path 142
- ECRC on the TX Path 143
- Enable PLL calibration 145
- Debugging 148
- Setting Up Simulation 149
- Use Third-Party PCIe Analyzer 150
- BIOS Enumeration Issues 151
- Address[31:2] 152
- Figure A-6: I/O Read Request 154
- 7 6 5 4 3 2 1 0 158
- Core Config 8 4 1 158
- Additional Information 160
- Date Version Changes Made 161
- How to Contact Altera 163
- Typographic Conventions 164
- Visual Cue Meaning 165
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