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Chapter 4: Functional Description 4–38
ALTDQ_DQS Megafunction Ports
© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
DQ Input Path Megafunction Ports
Table 4–15 summarizes all the ports on the megafunction that configure the DQ input
path. The possible values for <IO> are BIDIR_DQ and INPUT_DQ.
oct_reg_clk Input Optional GND This port feeds the full-rate clock signal to the
<IO>_OCT_FF:clk and <IO>_OCT_DDIO_OE:clk
ports.
output_dq_hr_oct_in
[2*n
o
-1..0]
Input Optional GND This port feeds the half-rate output DQ signal for the
OUTPUT_DQ_OCT_HR_DDIO_OUT:datainhi /
datainlo ports.
output_dq_oct_in
[n
o
-1..0]
Input Optional GND This port feeds the full-rate output DQ signal for the
OUTPUT_DQ_OCT_FF:d,
OUTPUT_DQ_OCT_DDIO_OE:oe,
OUTPUT_DQ_OCT_DELAY_CHAIN1:datain,
OUTPUT_DQ_OCT_DELAY_CHAIN2:datain, or
output_dq_oct_out port.
output_dq_oct_out
[n
o
-1..0]
Output Optional — This port outputs signal from the
OUTPUT_DQ_OCT_DELAY_CHAIN2:dataout,
OUTPUT_DQ_OCT_DELAY_CHAIN1:dataout,
OUTPUT_DQ_OCT_FF:q,
OUTPUT_DQ_OCT_DDIO_OE:dataout, or
output_dq_oct_in port.
Table 4–14. Megafunction Ports to Configure OCT Path (Part 2 of 2)
Port Name Type
Optional/
Required Default Description
Table 4–15. Megafunction Ports to Configure DQ Input Path (Part 1 of 2)
Port Name Type
Optional/
Required Default Description
bidir_dq_areset
[n
b
-1..0]
Input Optional GND This port is connected to all areset port in the
bidirectional DQ IO primitives that is used to
asynchronously reset the registers in those
primitives.
bidir_dq_hr_input_
data_out[4*n
b
-1..0]
Output Optional — This port outputs the half-rate DDR bidirectional DQ
signal from the
BIDIR_DQ_HALF_RATE_INPUT:dataout
port.
bidir_dq_input_data_in
[n
b
-1..0]
Input Optional GND This port feeds the bidirectional DQ signal for the
BIDIR_DQ_INPUT_DELAY_CHAIN:datain,
BIDIR_DQ_INPUT_FF:d,
BIDIR_DQ_DDIO_IN:datain, or
bidir_dq_input_data_out port.
bidir_dq_input_data_ou
t_high[n
b
-1..0]
Output Optional — This port outputs the full-rate DDR bidirectional DQ
signal (rising edge) from the
BIDIR_DQ_IPA_HIGH:dataout or
BIDIR_DQ_DDIO_IN:regouthi.
bidir_dq_input_data_ou
t_low[n
b
-1..0]
Output Optional — This port outputs the full-rate DDR bidirectional DQ
signal (falling edge) from the
BIDIR_DQ_IPA_LOW:dataout or
BIDIR_DQ_DDIO_IN:regoutlo.
- ALTDLL and ALTDQ_DQS 1
- Megafunctions User Guide 1
- UG-01032-5.0 2
- Contents 3
- 1. About these Megafunctions 5
- Features 6
- 2. Getting Started 7
- ALTOCT Megafunction 8
- Customized Controller Logic 8
- Simulate the Design 9
- Create Timing Constraints 9
- Adjust Constraints 10
- Generate the Megafunctions 11
- Settings Value 13
- Turned off 14
- Enable DQS delay chain 14
- 3. Parameter Settings 19
- [5..0] output port 20
- ALTDLL Parameter Editor 21
- ALTDQ_DQS Parameter Editor 23
- Reset/Config Ports 26
- ports on the megafunction 27
- — DQS_OFFSETCTRL_ 27
- inputs to be registered by 28
- signals of 28
- “DQ Input Path” on page 4–8 29
- 4. Functional Description 37
- ■ DQS Input Path 38
- ■ DQ Input Path 38
- ■ DQ Output/OE Path 38
- ■ DQS Output/OE Path 38
- ■ DQ/DQS OCT Path 38
- ALTDLL Megafunction 39
- ALTDQ_DQS Megafunction 40
- DQS Input Path 42
- DQ Input Path 44
- DQ Output/OE Path 46
- DQS Output/OE Path 48
- DQ/DQS OCT Path 50
- Delay Chains 51
- Deskew Delay Chains 52
- Note to Figure 4–13: 55
- Note to Figure 4–14: 55
- Note to Figure 4–15: 56
- Note to Figure 4–16: 56
- Note to Figure 4–17: 57
- DQS_CONFIG / IO_CONFIG Block 58
- ALTDLL Megafunction Ports 67
- ALTDQ_DQS Megafunction Ports 69
- DQ OE Path Megafunction Ports 78
- DQSn I/O Path Ports 79
- DQS_CONFIG/IO_CONFIG path 81
- RLDRAM interfaces 84
- Procedure 85
- 00 FF 00 FF 99
- ■ bidir_dq_io[0] 100
- A. Clear Box Generator 102
- Clear Box Generator Options 103
- Clear Box Parameters 104
- inputs are 108
- OUTPUT_DQ 114
- Additional Information 116
- Typographic Conventions 117
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