Altera ALTDLL Manual de usuario descargar pdf (Pagina 113)

A–12 Appendix A: Clear Box Generator

Clear Box Generator Options

ALTDLL and ALTDQ_DQS Megafunctions User Guide © February 2012 Altera Corporation

DQ_INPUT_REG_CLK_SOURCE Optional dqs_bus dqs_bus,

Core

If Core, <IO>_INPUT_FF:clk /

<IO>_DDIO_IN:clk port on the

primitive is fed by

dq_input_reg_clk port on the

megafunction

If dqs_bus, <IO>_INPUT_FF:clk

/ <IO>_DDIO_IN:clk port on the

primitive is fed by dqs_bus_out

port on the megafunction

DQ_INPUT_REG_CLK_USE_

CLKN

Optional FALSE FALSE, TRUE If TRUE, <IO>_DDIO_IN:clk port

on the primitive is fed by

dqs_bus_out port on the

megafunction and

<IO>_DDIO_IN:clkn port on the

primitive is fed by dqsn_bus_out

port on the megafunction

USE_DQ_IPA Optional FALSE FALSE, TRUE Instantiates <IO>_IPA_HIGH /

<IO>_IPA_LOW if TRUE

USE_DQ_IPA_PHASECTRLIN Optional FALSE FALSE, TRUE <IO>_IPA_HIGH.use_phasectr

lin port on the primitive

<IO>_IPA_LOW.use_phasectrl

in port on the primitive

DQ_IPA_PHASE_SETTING Optional 0 0..7 <IO>_IPA_HIGH.phase_settin

g port on the primitive

<IO>_IPA_LOW.phase_setting

port on the primitive

DQ_IPA_ADD_INPUT_CYCLE_

DELAY

Optional FALSE FALSE, TRUE,

DYNAMIC

<IO>_IPA_HIGH.add_input_cy

cle_delay port on the primitive

<IO>_IPA_LOW.add_input_cyc

le_

delay port on the primitive

DQ_IPA_BYPASS_OUTPUT_

Optional FALSE FALSE, TRUE <IO>_IPA_HIGH.bypass_outpu

<IO>_IPA_LOW.bypass_output

rt on the primitive

DQ_IPA_ADD_PHASE_

TRANSFER_REG

Optional FALSE FALSE, TRUE,

DYNAMIC

<IO>_IPA_HIGH.add_phase_

transfer_reg port on the primitive

<IO>_IPA_LOW.add_phase_

transfer_reg port on the primitive

Table A–7. Megafunction Parameters to Configure DQ Input Path (Part 2 of 3)

Parameter Name

Optional/

Required Default Legal Values Description

1 2 ... 108 109 110 111 112 113 114 115 116 117

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