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About the Viterbi IP Core
1
2014.12.15
UG-VITERBI
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Altera DSP IP Core Features
• Avalon
®
Streaming (Avalon-ST) interfaces
• DSP Builder ready
• Testbenches to verify the IP core
• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
Viterbi II IP Core Features
• High-speed parallel architecture:
• Performance of over 250 megabits per second (Mbps)
• Fully parallel operation
• Optimized block decoding and continuous decoding
• Low to medium-speed, hybrid architecture:
• Configurable number of add compare and select (ACS) units
• Memory-based architecture
• Wide range of performance; wide range of logic area
• Fully parameterized Viterbi decoder, including:
• Number of coded bits
• Constraint length
• Number of soft bits
• Traceback length
• Polynomial for each coded bit
• Variable constraint length
• Trellis coded modulation (TCM) option
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
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