Altera Stratix IV GX FPGA Development Board Manual de usuario descargar pdf (Pagina 23)

Chapter 2: Board Components 2–15

Configuration, Status, and Setup Elements

August 2012 Altera Corporation Stratix IV GX FPGA Development Board

Reference Manual

Figure 2–5 shows the PFL configuration.

Table 2–8 lists the flash memory map storage.

Figure 2–5. PFL Configuration

MAX II CPLD

EPM2210 System Controller

FPGA_DATA [7:0]

FPGA_DCLK

FLASH_A [25:1]

FLASH_D [15:0]

DATA [7:0]

DCLK

INIT_DONE

nSTATUS

nCONFIG

CONF_DONE

MSEL0

MSEL1

MSEL2

MSEL3

2.5 V

10 kΩ

nCE

CFI Flash

CONF_DONE LED

10 kΩ

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_A [25:1]

FLASH_D [15:0]

FLASH_CEn

FLASH_OEn

FLASH_WEn

FLASH_RSTn

FLASH_ADVn

MSEL [3:0]

FPGA_nCONFIG

FPGA_CONF_DONE

FSM Bus Interface

FLASH_RYBSYn

Rotary Switch

PGM [2:0]

FPGA_nSTATUS

USB_DISABLEn

2.5 V

10 kΩ

125 MHz

2.5 V

FLASH_ADVn

RESET_CONFIGn

CONF_DONE_LED

2.5 V

10 kΩ

FLASH_CLK

FLASH_RSTn

50 MHz

CONFIG_CLK

External JTAG Detect

Table 2–8. Flash Memory Map (Part 1 of 2)

Name Size (Kbyte) Address

Unused

0x03FF.FFFF

0x03FF.8000

0x03FF.7FFF

0x03FF.0000

0x03FE.FFFF

0x03FE.8000

0x03FE.7FFF

0x03FE.0000

User Software 24,320

0x03FD

FFFF

0x0282

0000

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 81 82

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