Altera Stratix III Development Board Manual de usuario Pagina 59
- Pagina / 82
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Chapter 2: Board Components 2–51
On-Board Memory
May 2013 Altera Corporation Stratix III 3SL150 Development Board
Reference Manual
J19 pin 87 Data bit 35
DDR2_DIMM_DQ35
SSTL-18 class I AP26
J19 pin 199 Data bit 36
DDR2_DIMM_DQ36
SSTL-18 class I AD21
J19 pin 200 Data bit 37
DDR2_DIMM_DQ37
SSTL-18 class I AE21
J19 pin 205 Data bit 38
DDR2_DIMM_DQ38
SSTL-18 class I AP23
J19 pin 206 Data bit 39
DDR2_DIMM_DQ39
SSTL-18 class I AN24
J19 pin 89 Data bit 40
DDR2_DIMM_DQ40
SSTL-18 class I AP27
J19 pin 90 Data bit 41
DDR2_DIMM_DQ41
SSTL-18 class I AN27
J19 pin 95 Data bit 42
DDR2_DIMM_DQ42
SSTL-18 class I AL28
J19 pin 96 Data bit 43
DDR2_DIMM_DQ43
SSTL-18 class I AK25
J19 pin 208 Data bit 44
DDR2_DIMM_DQ44
SSTL-18 class I AM26
J19 pin 209 Data bit 45
DDR2_DIMM_DQ45
SSTL-18 class I AL26
J19 pin 214 Data bit 46
DDR2_DIMM_DQ46
SSTL-18 class I AP29
J19 pin 215 Data bit 47
DDR2_DIMM_DQ47
SSTL-18 class I AM28
J19 pin 98 Data bit 48
DDR2_DIMM_DQ48
SSTL-18 class I AN30
J19 pin 99 Data bit 49
DDR2_DIMM_DQ49
SSTL-18 class I AM30
J19 pin 107 Data bit 50
DDR2_DIMM_DQ50
SSTL-18 class I AJ26
J19 pin 108 Data bit 51
DDR2_DIMM_DQ51
SSTL-18 class I AH27
J19 pin 217 Data bit 52
DDR2_DIMM_DQ52
SSTL-18 class I AM29
J19 pin 218 Data bit 53
DDR2_DIMM_DQ53
SSTL-18 class I AL29
J19 pin 226 Data bit 54
DDR2_DIMM_DQ54
SSTL-18 class I AJ29
J19 pin 227 Data bit 55
DDR2_DIMM_DQ55
SSTL-18 class I AJ27
J19 pin 110 Data bit 56
DDR2_DIMM_DQ56
SSTL-18 class I AF24
J19 pin 111 Data bit 57
DDR2_DIMM_DQ57
SSTL-18 class I AG24
J19 pin 116 Data bit 58
DDR2_DIMM_DQ58
SSTL-18 class I AF23
J19 pin 117 Data bit 59
DDR2_DIMM_DQ59
SSTL-18 class I AN31
J19 pin 229 Data bit 60
DDR2_DIMM_DQ60
SSTL-18 class I AH25
J19 pin 230 Data bit 61
DDR2_DIMM_DQ61
SSTL-18 class I AH26
J19 pin 235 Data bit 62
DDR2_DIMM_DQ62
SSTL-18 class I AP31
J19 pin 236 Data bit 63
DDR2_DIMM_DQ63
SSTL-18 class I AP30
J19 pin 42 Data bit 64
DDR2_DIMM_DQ64
SSTL-18 class I AH22
J19 pin 43 Data bit 65
DDR2_DIMM_DQ65
SSTL-18 class I AM23
J19 pin 48 Data bit 66
DDR2_DIMM_DQ66
SSTL-18 class I AJ23
J19 pin 49 Data bit 67
DDR2_DIMM_DQ67
SSTL-18 class I AJ24
J19 pin 161 Data bit 68
DDR2_DIMM_DQ68
SSTL-18 class I AK22
J19 pin 162 Data bit 69
DDR2_DIMM_DQ69
SSTL-18 class I AL23
J19 pin 167 Data bit 70
DDR2_DIMM_DQ70
SSTL-18 class I AL25
J19 pin 168 Data bit 71
DDR2_DIMM_DQ71
SSTL-18 class I AK24
J19 pin 6 Data strobe bit 0
DDR2_DIMM_DQS_N0
SSTL-18 class I AL11
J19 pin 15 Data strobe bit 1
DDR2_DIMM_DQS_N1
SSTL-18 class I AN9
Table 2–45. DDR2 DIMM Interface I/O Signals (Part 3 of 4)
Board Reference Description
Schematic
Signal Name
I/O Standard
Stratix III
Pin Number
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- General Description 7
- Handling the Board 8
- 2. Board Components 9
- MSEL0 to GND 10
- Jumper (J13) 10
- Board Overview 11
- Featured FPGA (U22) 12
- Device Support 14
- I/O Resources 14
- MAX II CPLD 16
- FPGA Programming Over USB 25
- Notes to Table 2–7: 26
- Status Elements 27
- Board Specific LEDs 28
- Power Display 29
- JTAG Control DIP Switch 29
- Power Select Rotary Switch 31
- Clocking Circuitry 33
- Stratix III FPGA Clock Inputs 34
- General User Interfaces 36
- Note to Table 2–21: 37
- General User-Defined LEDs 38
- HSMC User-Defined LEDs 39
- User 7-Segment Display 40
- Power 7-Segment Display 41
- Character LCD 41
- Graphics LCD 43
- Radio at www.njr.co.jp 45
- Speaker Header 46
- Components and Interfaces 47
- High-Speed Mezzanine Cards 49
- On-Board Memory 56
- DDR2 SDRAM DIMM 57
- DDR2 SDRAM Devices 61
- QDRII+ SRAM 63
- Flash Memory 71
- Power Supply 75
- Power Measurement 76
- Notes to Table 2–60: 78
- Note to Table: 80
- Additional Information Info–3 81
- Typographic Conventions 81
- Info–4 Additional Information 82
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