Altera Quartus II Scripting Manual de usuario Pagina 73
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Valorado. / 5. Basado en revisión del cliente
Chapter 2: Command-line Executables 2–47
quartus_map
© July 2013 Altera Corporation Quartus II Scripting Reference Manual
--family=<device family>
Option to target the specified device family. If the "--part" option is not used, the part is set to Auto.
The family name should not contain any spaces, for example, --family=APEXII. If you need to add space
between words in the family name, make sure that you enclose the words in double quotation marks "", for
example, --family="APEX II".
--generate_cmp_file=<design file>
Option to create a default VHDL Component File (.cmp) that represents the entities in the specified Text
Design File (.tdf), VHDL Design File (.vhd), Verilog Design File (.v), EDIF Input File (.edf), or Block Design
File (.bdf), CusP file (.cpp) and MATLAB File (.mdl).
--generate_functional_sim_netlist
Option to prepare the databases necessary for functional simulation.
--generate_inc_file=<design file>
Option to create a default AHDL Include File (.inc) that represents the entities in the specified Text Design
File (.tdf), VHDL Design File (.vhd), Verilog Design File (.v), EDIF Input File (.edf), or Block Design File
(.bdf).
--generate_inst_file=<design file>
Option to create a default Verilog Instantiation File (.inst) that represents the entities in the specified Text
Design File (.tdf), VHDL Design File (.vhd), Verilog Design File (.v), EDIF Input File (.edf), Block Design
File (.bdf), CusP file (.cpp) or MATLAB file (.mdl).
--generate_symbol=<design file>
Option to create a Block Symbol File (.bsf) that represents the entities in the specified Text Design File
(.tdf), VHDL Design File (.vhd), Verilog Design File (.v), EDIF Input File (.edf), or Block Design File (.bdf).
--ignore_carry_buffers[=on|off]
Option to ignore CARRY_SUM buffers that are instantiated in the design. (This option also applies to
MAX+PLUS II-style CARRY buffers.)
--ignore_cascade_buffers[=on|off]
Option to ignore CASCADE buffers that are instantiated in the design.
--incremental_compilation=<off|full_incremental_compilation>
Option to specify the incremental compilation mode.
The following table displays available values:
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- MNL-Q2101904-9.1.1 2
- Contents 3
- Contents v 5
- Contents vii 7
- Contents ix 9
- Contents xi 11
- Contents xiii 13
- Contents xv 15
- About this Reference Manual 17
- Typographic Conventions 18
- Reference Manual 19
- Command-Line Executables 20
- Overview 21
- Tcl Commands 23
- Quartus_sta 24
- Quartus_staw 24
- Tcl Console 24
- Related Documentation 25
- 2. Command-line Executables 27
- --generate_hc_files 33
- --generate_hc_pll_delay 33
- --hc_min_archive 34
- --hc_ready 34
- --hc_review 35
- --post_map[=on 40
- --update_mif 41
- --vqm[=<.vqm file>] 41
- --write_rcf_for_vqm[=on 41
- --operation=<pb 45
- --option=<filename> 45
- --voltage=<voltage> 46
- String Description 47
- Examples 50
- --post_syn[=on 52
- --rtl[=on 52
- --hc[=on 52
- --post_fit[=on 52
- --board_symbol[=on 55
- --board_timing[=on 55
- --format=<NONE> 55
- --gen_script=<NONE> 56
- --gen_testbench 56
- --glitch_filtering[=on 56
- --resynthesis[=on 56
- --simulation[=on 57
- --timing_analysis[=on 57
- --vcd_type=<NONE> 59
- --check_ios 61
- --check_netlist 61
- --fmax=<time unit> 62
- --incremental_signaltap 62
- --inner_num=<value> 62
- --io_smart_recompile 63
- --one_fit_attempt[=on 63
- --part=<device part> 63
- --seed=<value> 64
- --signalprobe 64
- --tdc[=on 64
- --compress 67
- -a=<action to perform> 68
- --enumerate_hardware 70
- --loquacious 70
- --lib_path=<path> 74
- --parallel[=on 74
- --part=<device> 74
- --partition=<NONE> 74
- --source=<source file> 75
- --update_wysiwyg_parameters 75
- --verilog_macro=<NONE> 75
- --haltcc 78
- --initcfg 78
- --estimate_power[=on 81
- --no_input_file 82
- --archive 85
- --determine_smart_action 86
- --prepare 92
- --qboard 92
- --qinstall 93
- --qslave 93
- --relcon 94
- --restore 94
- --simlib_comp 95
- -g[=on 98
- --bank=<bank index> 98
- --grouping[=on 99
- --sso_inputs[=on 99
- Value Description 102
- --report_script=<NONE> 107
- --sdc=<NONE> 107
- --speed=<NONE> 107
- --voltage=<value_in_mV> 108
- --create_signaltap_hdl_file 110
- -c=<revision name> 110
- --combined_model[=on 114
- --create_timing_netlist 114
- --delay_annotation_only 114
- --tao[=<.tao file>] 116
- --tao_summary 116
- --tco=<time unit> 116
- --th=<time unit> 116
- --timing_analysis_only 116
- --tpd=<time unit> 117
- --tristate 117
- --tsu=<time unit> 117
- --zero_ic_delays 117
- -f=<argument file> 118
- --help[=<option 119
- --lower_priority 119
- --version 119
- Common Options 120
- Return Code Description 121
- 0 Execution was successful 121
- --rev=<revision name> 122
- -p[=on 123
- Settings File Options 124
- 2. Compiler database 127
- -t=<script file> 128
- --script=<script file> 128
- Tcl Options 129
- ■ quartus_tan 141
- Description 145
- ■ quartus 159
- ■ quartus_cdb 159
- <position>: Position 182
- <device>: Device name 225
- <family>: Family name 226
- <part>: Part name 227
- ■ quartus_sh 234
- ■ quartus_sta 234
- ■ quartus_stp 254
- # Close device 279
- $bus_name 298
- # Disables natural bus naming 298
- <command>: Command 311
- ■ export_assignments 317
- ## Close the project if open 350
- project_close 350
- # Using wildcards 358
- TSU_REQUIREMENT 2ns 368
- ■ quartus_map 401
- as an absolute time shift 418
- ■ quartus_sim 474
- Example 12 479
- Example 13 479
- Example 14 479
- Example 15 479
- Example 16 479
- Example 3 490
- Example 4 490
- Groups the specified signals 494
- -phase] [-rise] 523
- Option Destination Tool 551
- -chip Chip Planner 551
- -rpe Resource Property Editor 551
- -tmv Technology Map Viewer 551
- 0.100 -detail full_path 570
- (empty) Unknown transition 584
- R Rising output 584
- F Falling output 584
- Reports unconstrained paths 591
- MHz MegaHertz 625
- GHz GigaHertz 625
- Time Unit Description 625
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