Altera Nios Development Board Stratix II Edition Manual de usuario descargar pdf (Pagina 39)

Altera Corporation Reference Manual 2–29

May 2007 Nios Development Board Stratix II Edition

Board Components

Mictor

Connector (J25)

The Mictor connector (J25) can be used to transmit up to 27 high-speed

I/O signals with very low noise via a shielded Mictor cable. J25 can be

used as a debug port for the Nios II processor or as a general-purpose I/O

connector to the FPGA. Twenty-five of the Mictor connector signals are

used as data, and two signals are used as clock input and clock output.

Most pins on J25 connect to I/O pins on the FPGA (U60). For systems that

do not use the Mictor connector for debugging the Nios II processor, any

on-chip signals can be routed to I/O pins and probed at J25. External

scopes and logic analyzers can connect to J25 and analyze a large number

of signals simultaneously.

AC6 52 JH1 pmc_be_n0

AF6 43 JH2 pmc_be_n1

AA10 32 JH2 pmc_be_n2

AC7 26 JH1 pmc_be_n3

AF8 43 JH1 pmc _par

AE14 13 JH1 pmc_clk

AA11 39 JH2 pmc_perr_n

AC10 42 JH2 pmc_serr_n

AA12 37 JH1 pmc_devsel_n

AD9 38 JH2 pmc_stop_n

AC14 36 JH1 pmc_irdy_n

AB9 4 JH1 pmc_inta_n

AB7 5 JH1 pmc_intb_n

V10 6 JH1 pmc_intc_n

AA8 9 JH1 pmc_intd_n

AD14 13 JH2 pmc_reset_n

AE9 33 JH1 pmc_frame_n

AF15 35 JH2 pmc_trdy_n

AB10 25 JH2 pmc_idsel

AD6 16 JH1 pmc_gnt_n

AD5 17 JH1 pmc_req_n

AD3 40 JH1 pmc_lock_n

AF3 47 JH2 pmc_m66en

AE23 64 JH1 pmc_req64_n

Table 2–15. PMC Connector Pin Table (Continued)

FPGA Pin JH1 & JH2 Pin Connector Board Net Name

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 61 62

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Altera Nios Development Board Stratix II Edition Manual de usuario Pagina 39