Altera LVDS SERDES Manual de usuario descargar pdf (Pagina 13)

DescriptionValueParameter

When enabled, this parameter exposes the rx_

bitslip_reset port (one input per channel), which

you can use to reset the bitslip.

—Enable rx_bitslip_reset port

When enabled, this parameter exposes the rx_

bitslip_max port (one output per channel). When

asserted, the next rising edge of rx_bitslip_ctrl

resets the latency of the bitslip to zero.

—Enable rx_bitslip_max port

Sets the maximum latency that can be injected using

bitslip. When it reaches that value, it rolls over and

the rx_bitslip_max signal is asserted. The default

value is 10.

Altera recommends setting this

parameter to a value equal to or greater

than the deserialization factor.

Note:

3, 4, 5, 6, 7, 8, 9,

10, 11

Bitslip rollover value

DPA Settings

When enabled, the IP core exposes the rx_dpa_

reset port, which you can use to reset the DPA

logic of each channel independently. Formerly

known as rx_reset.

—Enable rx_dpa_reset port

When enabled, user logic drives the rx_fifo_reset

port which you can use to reset the DPA-FIFO

block.

—Enable rx_fifo_reset port

When enabled, the IP core exposes the rx_dpa_

hold input port (one input per channel). When set

high, the DPA logic in the corresponding channel

does not switch sampling phases. The rx_dpa_hold

port is formerly known as rx_dpll_hold port.

—Enable rx_dpa_hold port

Altera Corporation

Altera LVDS SERDES IP Core User Guide

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2014.08.18

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Altera LVDS SERDES Manual de usuario Pagina 13

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