Altera LVDS SERDES Manual de usuario descargar pdf (Pagina 11)

Parameter Settings

You can parameterize the Altera LVDS SERDES IP core using the IP Parameter Editor.

General Settings Tab

DescriptionValueParameter

Specifies the functional mode of the interface.• TX

• RX Non-DPA

• RX DPA-FIFO

• RX Soft-CDR

Functional mode

Specifies the number of serial channels in the

interface.

• Decrement one channel for the dedicated

reference clock pin (refclk) for TX, RX

Non-DPA, and RX DPA. Not using the

dedicated reference clock pin may

contribute to higher jitter.

• Decrease by one channel for the TX

outclock pin (tx_outclock) if used.

• 1 to 72 for TX

• 1 to 24 for RX Non-

DPA

• 1 to 24 for RX DPA-

FIFO

• 1 to 12 for RX Soft-

CDR

Number of channels

Specifies the data rate (in Mbps) of a single

serial channel. The value is dependent on the

Functional mode parameter settings.

150.0 to 1600.0Data rate

Specifies the serialization rate or deserializa-

tion rate for the LVDS interface.

3, 4, 5, 6, 7, 8, 9, and 10SERDES factor

When enabled, the IP core bypasses the PLL

and the interface is driven with a clock pin.

This feature is not supported in

the current version of the Quartus

II software.

Note:

—

Use clock-pin drive

When enabled, the IP core uses legacy top-

level names that are compatible with

ALTLVDS_TX and ALTLVDS_RX IP cores.

—

Use backwards-compatible port

names

Altera Corporation

Altera LVDS SERDES IP Core User Guide

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Parameter Settings

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2014.08.18

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