Altera Internal Memory (RAM and ROM) IP Core Manual de usuario Pagina 4

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About RAM: 1-PORT, RAM: 2-PORT, ROM: 1-
PORT, and ROM: 2-PORT IP Cores
1
2014.12.17
UG-01068
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The Quartus
®
II software automatically selects one of megafunction IP cores to implement memory
modes. The selection depends on the target device, memory modes, and features of the RAM and ROM.
Table 1-1: IP Cores for Embedded Memory Blocks
This table lists the IP cores for embedded memory blocks.
IP Core Memory Mode
RAM: 1-PORT Single-port RAM
RAM: 2-PORT Dual-port RAM
ROM: 1-PORT Single-port ROM
ROM: 2-PORT Dual-port ROM
Embedded Memory Features
The embedded memory blocks provide the following features:
Memory Modes Configuration
Memory Block Types
Write and Read Operations Triggering
Port Width Configuration
Mixed-width Port Configuration
Maximum Block Depth Configuration
Clocking Modes and Clock Enable
Address Clock Enable
Byte Enable
Asynchronous Clear
Read Enable
Read-During-Write
Power-Up Conditions and Memory Initialization
Error Correction Code
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