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3–20 Chapter 3: Functional Description
Interfaces & Signals
DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation
Writes
Figure 3–13 on page 3–20 shows three write requests of different sizes, the first two to
sequential addresses and the third to a new row and bank. The controller allows you
to use any burst length up to the maximum burst length set on the memory device.
For example, if you select burst length of 8 for your DDR SDRAM memory, the
controller allows bursts of length 1, 2, 3, and 4 (2, 4, 6, and 8 on the DDR SDRAM
side).
1 The concept is similar for DDR2 SDRAM although only burst lengths 1 and 2 (2 and 4
on the DDR2 SDRAM side) are available.
Figure 3–13. Writes
Notes to Figure 3–13:
(1) The local_cs_addr, local_row_addr, local_bank_addr, and local_col_addr signals are a representation of the
local_addr signal.
(2) DDR Command shows the command that the command signals (ddr_ras_n, ddr_cas_n and ddr_we_n) are issuing.
clk
local_read_req
local_write_req
local_ready
local_size
local_cs_addr
(
1
)
local_row_addr (
1
)
local_bank_addr (
1
)
local_col_addr (
1
)
local_wdata_req
local_wdata
local_be
ddr_cs_n
ddr_cke
ddr_a
ddr_ba
DDR Command (
2
)
ddr_ras_n
ddr_cas_n
ddr_we_n
ddr_dm(0)
ddr_dq
ddr_dqs(0)
1 2 44
1 3 03
010 210 000210
1 3 03
020 021 030 000030
9275FF45 1A27 C510A84BD259 A04AD259
2 1 3 23
F
D F D F 7 F 7 F7
F
000
010 000 040 042 0000 210 000 060 000060
0
1 0 1 0 3 0 3 03
NOP
ACT NOP WR NOP ACT NOP WR NOPWR
DDR SDRAM
Interface
Local Interface
[1]
[3]
[2] [5][4] [6]
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Software Version: 9.0 1
- Document Date: March 2009 1
- UG-DDRSDRAM-10.0 2
- Contents 3
- 1. About This Compiler 5
- Features 6
- General Description 6
- Note to Figure 1–1: 7
- Note to Table 1–3: 8
- Installation and Licensing 9
- OpenCore Plus Evaluation 10
- 2. Getting Started 11
- SOPC Builder Design Flow 12
- Parameterize 14
- Constraints 15
- Add/Update Component 15
- Create Your Top-Level Design 16
- Edit the PLL 17
- Program a Device 18
- Figure 2–1. System Naming 24
- Set Up Simulation 25
- Generate 25
- Simulate the Example Design 27
- Notes to Table 2–2: 29
- Notes to Table 2–3: 30
- Notes to Table 2–4: 31
- Compile the Example Design 32
- Implement Your Design 34
- Set Up Licensing 35
- Control Logic 37
- Datapath 38
- Device-Level Description 41
- Figure 3–3. Datapath Timing 42
- Designing Your Own Controller 43
- DQS Group Block Diagrams 44
- Notes to Figure 3–4: 45
- Notes to Figure 3–5: 46
- Notes to Figure 3–6: 47
- Notes to Figure 3–7: 48
- PLL Configurations 49
- Stratix II Device 50
- Stratix Device 51
- Cyclone II Device 51
- Cyclone Device 51
- DLL Configurations 52
- Example Design 52
- Notes to Table 3–5: 53
- Interface Description 55
- Figure 3–13. Writes 56
- Interfaces & Signals 57
- DDR SDRAM 58
- Interface 58
- Local Interface 58
- [1] [3][2] [5][4] 58
- [1] [2] [3] [4] [6][5] 59
- User Refresh Control 60
- 200 clock cycles 63
- Note to Table 3–7: 65
- Parameters 67
- Controller 69
- Note to Table 3–15: 71
- Controller Timings 73
- Memory Timings 74
- Board Timings 75
- Project Settings 76
- Manual Timings 77
- Simulation Testing 77
- Hardware Testing 77
- (MT46V8M16-75Z) 78
- A. Manual Timing Settings 79
- Resynchronization 82
- Resynchronization Registers 83
- Notes to Figure A–2: 84
- Notes to Figure A–3: 85
- Notes to Figure A–4: 86
- Notes to Table A–5: 87
- Note to Figure A–5: 87
- DQS Postamble 88
- Postamble Logic 89
- System Clock 90
- Postamble 90
- Examples 91
- Board, Cyclone II Edition 95
- D. Maximizing Performance 101
- Adjust the PLL Phases 102
- Assign Pins 102
- Place the Fedback PLL 102
- Update the PLL Phases 103
- Additional Information 105
- Typographic Conventions 106
- Preliminary 106
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