Altera DDR SDRAM Controller Manual de usuario descargar pdf (Pagina 51)

Chapter 3: Functional Description 3–15

Device-Level Description

Figure 3–10 shows the Cyclone II configuration for use with any PLL multiply or

divide ratios including a ratio of one.

Figure 3–11 on page 3–15 shows the Cyclone configuration.

Figure 3–9. Stratix PLL Configuration (Note 1)

Note to Figure 3–9:

(1) In most cases, clk or write_clk are used as the resynchronization and postamble clocks, therefore you need not use a separate clock output

from the PLL.

Stratix Device

clk_to_sdram

clk_to_sdram_n

DDR SDRAM

Controller

Stratix DLL

dqs_ref_clk

altddio

Note 1

clock_source

Enhanced PLL

clk

write_clk

resynch_clk or

capture_clk

postamble_clk

DDR SDRAM

Figure 3–10. Cyclone II PLL Configuration

Cyclone II Device

clock_source

clk_to_sdram

clk_to_sdram_n

DDR SDRAM

Controller

PLL

clk

write_clk

resynch_clk

altddio

DDR SDRAM

Figure 3–11. Cyclone PLL Configuration

Cyclone Device

clock_source

clk_to_sdram

clk_to_sdram_n

DDR SDRAM

Controller

PLL

clk

write_clk

altddio

DDR SDRAM

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 105 106

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