Altera PHYLite Manual de usuario Pagina 54

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Figure 27: ALTDQ_DQS2 Settings for Bidirectional Type DQ and DQS
Note: The DQS enable block must be enabled for NAND Flash, which has bidirectional strobe.
Note: DQS phase shift is set to 135° to gain maximum margin (due to the memory clock is slower than
the DLL’s minimum frequency)
Figure 28: ALTDQ_DQS2 settings for output type (Addr/Cmd)
Note:
The settings in the figure are for the address/command lines.
54
Implementation Using the ALTDQ_DQS2 IP Core
ug_altera_phylite
2015.01.16
Altera Corporation
Altera PHYLite for Parallel Interfaces IP Core User Guide
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