Altera 10-Gbps Ethernet MAC MegaCore Function Manual de usuario descargar pdf (Pagina 130)

Chapter 9: Interface Signals 9–11

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

9.0.4. GMII Signals

Table 9–5 shows the GMII signals. These signals are applicable only if you enable

1G/10GbE MAC or multi-speed 10M-10GbE MAC. For 1 Gbps, 10 Mbps, and

100 Mbps mode, the MAC uses the

gmii_tx_clk

and

gmii_rx_clk

from the PHY IP.

9.0.5. MII Signals

Table 9–6 shows the MII signals. These signals are applicable only if you enable

multi-speed 10M-10GbE MAC. For 10 Mbps and 100 Mbps modes, the MAC uses the

gmii_tx_clk

and

gmii_rx_clk

from the PHY IP.

Table 9–5. GMII Signals

Signal Direction Width Description

gmii_rx_clk_clk

Input –

125-MHz receive clock. Provides the timing reference

for the GMII receive interface.

gmii_rx_d[]

Input 8 The GMII receive data bus

gmii_rx_dv

Input 1 This signal indicates that the RX data is valid.

gmii_rx_err

Input 1

The PHY asserts this signal to indicate that the

current frame contains error.

gmii_tx_clk_clk

Input –

125-MHz transmit clock. Provides the timing

reference for the GMII transmit interface.

gmii_tx_d[]

Output 8 The GMII transmit data bus.

gmii_tx_en

Output 1 This signal indicates that the TX data is valid.

gmii_tx_err

Output 1

This signal is asserted to indicate to the PHY that the

transmitted frame is invalid.

Table 9–6. MII Signals

Signal Direction Width Description

mii_rx_d[]

Input 4 The MII receive data bus

mii_rx_dv

Input 1 This signal indicates that the RX data is valid.

mii_rx_err

Input 1

The PHY asserts this signal to indicate that the

current frame contains error.

rx_clkena

Input 1

The RX clock enable provided by the PHY IP to the

MAC. This clock divides

gmii_rx_clk_clk

down to

25 MHz for 100 Mbps mode and 2.5 MHz for

10 Mbps mode.

rx_clkena_half_rate

Input 1

The RX half-clock enable provided by the PHY IP to

the MAC. This clock divides

gmii_rx_clk_clk

down

to 12.5 MHz for 100 Mbps mode and 1.25 MHz for

10 Mbps mode.

mii_tx_d[]

Output 4 The MII transmit data bus.

mii_tx_en

Output 1 This signal indicates that the TX data is valid.

mii_tx_err

Output 1

This signal is asserted to indicate to the PHY that the

transmitted frame is invalid.

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