Altera DE2-115 Guía de usuario descargar pdf (Pagina 52)

SFSU - Embedded Systems Tutorial Nano- Electronics & Computing Research Lab

Chapter 4 : Video Generation for Text

Display on T-Pad

Introduction

In this chapter, the ALU will be displayed on T-Pad. Switches perform different operation of the ALU.

With switches, different numbers can be displayed and also their ALU operations can be performed.

Hardware

The T-Pad features an 8-inch Amorphous-TFT-LCD panel. The LCD Screen module offers resolution of

(800x600) to provide users the best display quality for developing applications. The LCD panel supports

18-bit parallel RGB data interface.

The hardware is implemented using Altera IP cores on SOPC builder. A phase locked loop (Alt PLL) has

been used to generate the required clocking for the whole system. In this system a 100Mhz clock for the

Nios-II/f have been used, another 100Mhz with -65 phase shift is used to clock the SDRAM in addition to

the required 40Mhz clock for the VGA controller. The figure above shows the block diagram of the

hardware that is implemented in the SOPC builder.

Character Buffer

DMA

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 106 107

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Altera DE2-115 Guía de usuario Pagina 52