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Valorado. / 5. Basado en revisión del cliente
6–6 Altera Corporation
Nios II Processor Reference Handbook October 2007
JTAG Debug Module Revisions
Nios II/e Core
Table 6–5 lists revisions to the Nios II/e core.
JTAG Debug
Module
Revisions
JTAG debug module revisions augment the debug capabilities of the
Nios II processor, or fix bugs isolated within the JTAG debug module
logic.
Table 6–5. Nios II/e Core Revisions
Version Release Date Notes
7.2 October 2007
Implemented the
jmpi instruction.
7.1 May 2007 No changes.
7.0 March 2007 No changes.
6.1 November 2006 No changes.
6.0 May 2006 No changes.
5.1 October 2005 No changes.
5.0 May 2005
● Full support for HardCopy devices (previous versions required a work
around to support HardCopy devices).
1.1 December 2004
Added
cpuid control register.
1.01 September 2004
● Bug Fix:
The SOPC Builder top-level system module included an extra,
unnecessary output port for systems with very small address spaces.
1.0 May 2004 Initial release of the Nios II/e core.
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 3
- Chapter 3. Programming Model 4
- Section II. Appendices 5
- Altera Corporation vii 7
- Chapter Revision Dates 9
- About This Handbook 11
- How to Find 12
- Further 12
- Information 12
- How to Contact 12
- Typographical 13
- Conventions 13
- Typographical Conventions 14
- Section I. Nios II 15
- Processor 15
- 1. Introduction 17
- Getting Started 18
- Customizing 19
- Nios II 19
- Configurable 20
- Soft-Core 20
- Concepts 20
- Standard Peripherals 21
- Custom Peripherals 21
- OpenCore Plus 22
- Evaluation 22
- 1–8 Altera Corporation 24
- Document Revision History 24
- 2. Processor Architecture 25
- Implementation 26
- Register File 27
- Arithmetic Logic 28
- Floating Point Instructions 29
- Reset Signals 30
- Exception and 30
- Interrupt 30
- Controller 30
- ALT_CI_EXCEPTION_VECTOR_N 31
- Memory and I/O 32
- Organization 32
- Instruction and Data Buses 33
- Memory and Peripheral Access 34
- Instruction Master Port 34
- Data Master Port 35
- Effective Use of Cache Memory 36
- Cache Bypass Methods 37
- Address Map 38
- Download and Execute Software 40
- Software Breakpoints 40
- Hardware Breakpoints 40
- Hardware Triggers 40
- Armed Triggers 41
- Execution vs. Data Trace 42
- Trace Frames 43
- 3. Programming Model 45
- Control 46
- Registers 46
- Operating 48
- Exception 49
- Processing 49
- Reset Exceptions 50
- Processing a Break 51
- Returning From a Break 52
- Altera Corporation 3–9 53
- Programming Model 53
- Trap Instruction 54
- Break Instruction 54
- Unimplemented Instruction 54
- Other Exceptions 55
- Exceptions 56
- Nested Exception Precautions 57
- Return Address Considerations 57
- Memory and 58
- Peripheral 58
- Categories 59
- Move Instructions 61
- Comparison Instructions 61
- Shift and Rotate Instructions 62
- Program Control Instructions 63
- Other Control Instructions 64
- 4. Instantiating the Nios II 67
- Processor in SOPC Builder 67
- Core Nios II 68
- Core Selection 69
- Multiply and Divide Settings 69
- Reset Vector 70
- Exception Vector 70
- Altera Corporation 4–5 71
- Caches and 72
- Interfaces Page 72
- Instruction Master Settings 73
- Data Master Settings 74
- Advanced 75
- Features Page 75
- Module Page 76
- Feature Description 77
- Debug Level Settings 78
- Break Vector 79
- Instructions 80
- Altera Corporation 4–15 81
- 4–16 Altera Corporation 82
- Custom Instructions Page 82
- Altera Corporation 4–17 83
- 4–18 Altera Corporation 84
- 5. Nios II Core 89
- Implementation Details 89
- Feature Core 90
- Nios II/e Nios II/s Nios II/f 90
- Device Family 91
- Nios II/f Core 91
- Overview 92
- Instruction and Data Caches 94
- 31... ...210 95
- Bursting 96
- Nios II/s Core 100
- Arithmetic Logic Unit 101
- Shift and Rotate Performance 102
- Instruction Cache 103
- Execution Pipeline 104
- Pipeline Stalls 105
- Branch Prediction 105
- Exception Handling 106
- JTAG Debug Module 106
- Unsupported Features 106
- Nios II/e Core 107
- Instruction Execution Stages 108
- Instruction Performance 108
- Referenced 109
- Documents 109
- Document 110
- Revision History 110
- 6. Nios II Processor Revision 111
- Architecture 112
- Revisions 112
- Core Revisions 113
- Version Release Date Notes 114
- JTAG Debug 116
- 7. Application Binary 119
- Interface 119
- Alignment 120
- Register Usage 120
- Frame Pointer Elimination 122
- Call Saved Registers 122
- Further Examples of Stacks 123
- Function Prologs 124
- Prolog Variations 125
- Arguments and 126
- Return Values 126
- 8. Instruction Set Reference 129
- Instruction 132
- Altera Corporation 8–5 133
- Instruction Set Reference 133
- Assembler 134
- Instruction Set 136
- Reference 136
- 31..28 155
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