Altera Triple Speed Ethernet MegaCore Function Manual de usuario Pagina 213

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Packet Classifier Signals
Packet Classifier Common Clock and Reset Signals
Table E-1: Clock and Reset Signals for the Packet Classifier
DescriptionWidthDirectionSignal
156.25-MHz register access reference clock.1Inputclk
Assert this signal to reset the clock.1Inputreset
Packet Classifier Avalon-ST Interface Signals
Table E-2: Avalon-ST DataIn Interface Signals for the Packet Classifier
DescriptionWidthDirectionSignal
The Avalon-ST input frames.
1Inputdata_sink_sop
1Inputdata_sink_eop
1Inputdata_sink_valid
1Outputdata_sink_ready
64Inputdata_sink_data
3Inputdata_sink_empty
1Inputdata_sink_error
Table E-3: Avalon-ST DataOut (Source) Interface Signals for the Packet Classifier
DescriptionWidthDirectionSignal
The Avalon-ST output frames.
1Inputdata_src_sop
1Inputdata_src_eop
1Inputdata_src_valid
1Outputdata_src_ready
64Inputdata_src_data
3Inputdata_src_empty
1Inputdata_src_error
Packet Classifier
Altera Corporation
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UG-01008
Packet Classifier Signals
E-2
2014.06.30
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