Altera PowerPlay Early Power Estimator for Altera CPLDs Manual de usuario descargar pdf (Pagina 17)

Chapter 2: PowerPlay Early Power Estimator Worksheets 2–7

Power Estimation Using the PowerPlay Early Power Estimator

December 2010 Altera Corporation PowerPlay Early Power Estimator for Altera CPLDs User Guide

Logic Section

A design is a combination of several design modules operating at different

frequencies and toggle rates. Each design module can have a different amount of

logic. For the most accurate power estimation, partition the design into different

design modules. Each row in the Logic section of the PowerPlay EPE spreadsheet

represents a separate design module.

Figure 2–5 shows the Logic section in the PowerPlay EPE spreadsheet.

Tab le 2–7 lists the parameters in the Logic section of the PowerPlay EPE spreadsheet.

Figure 2–5. Logic Section in the PowerPlay EPE Spreadsheet

Table 2–7. Logic Section Information (Part 1 of 2)

Column Heading Description

Logic Module Specify a name for each module of the design. This is an optional value.

Clock Freq (MHz)

Enter a clock frequency (in MHz). This value is limited by the maximum frequency specification

for the device families.

100 MHz with a 12.5% toggle means that each look-up table (LUT) or flipflop output toggles

12.5 million times per second (100  12.5%).

# LEs Enter the number of LEs in this module.

Toggle %

Enter the average percentage of logic toggling on each clock cycle. The toggle percentage

ranges from 0 to 100%. Typically, the toggle percentage is 12.5%, which is the toggle

percentage of a 16-bit counter. To ensure you do not underestimate the toggle percentage, use

a higher toggle percentage. Most logic only toggles infrequently; therefore, toggle rates of less

than 50% are more realistic.

For example, a

TFF

with its input tied to V

has a toggle rate of 100% because its output is

changing logic states on every clock cycle (refer Figure 2–6). Figure 2–7 shows an example of

a 4-bit counter. The first

TFF

with LSB output

cout0

has a toggle rate of 100% because the

signal toggles on every clock cycle. The toggle rate for the second

TFF

with output

cout1

50% because the signal only toggles on every two clock cycles. Consequently, the toggle rate

for the third

TFF

with output

cout2

and the fourth

TFF

with output

cout3

are 25% and 12.5%,

respectively. Therefore, the average toggle percentage for this 4-bit counter is

(100 + 50 + 25 + 12.5)/4 = 46.875%.

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Altera PowerPlay Early Power Estimator for Altera CPLDs Manual de usuario Pagina 17

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