Altera Partial Reconfiguration IP Core Manual de usuario descargar pdf (Pagina 8)

Partial Reconfiguration IP Core Ports

I/O Port List for PR IP Core

Table 1: Clock/Reset Ports

These options are always available.

Port Name Width Direction Function

nreset

1

Input Asynchronous reset for the PR

IP core. Set high to enable partial

reconfiguration. Set low to

prevent partial reconfiguration

and reset the state machine in

the PR IP core.

clk

1

Input User input clock to the PR IP

core.

This signal is ignored during

JTAG debug operations.

Table 2: Conduit Interface

This option is always available.

Port Name Width Direction Function

freeze

1

Output Active high signal used to freeze

the PR interface signals of the

region undergoing partial

reconfiguration. De-assertion of

this signal indicates the end of

PR operation.

8

Partial Reconfiguration IP Core Ports

UG-PARTRECON

2015.05.04

Altera Corporation

Partial Reconfiguration IP Core

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