Altera Parallel Flash Loader IP Manual de usuario descargar pdf (Pagina 29)

Type Port Constraint Type Delay Value

Output asynchro‐

nous

fpga_nconfig set_false_path —

pfl_flash_access_request set_false_path —

flash_nce set_false_path —

flash_nwe set_false_path —

flash_noe set_false_path —

flash_addr set_false_path —

Bidirectional

synchronous

flash_data

• Normal read mode:

set_false_path

• Burst read mode:

set_input_delay

Burst read mode:

Board delay from fpga_dclk

pin of the CPLD to DCLK pin of

the FPGA

Output synchro‐

nous

fpga_data set_input_delay Board delay + T

of the FPGA

fpga_dclk set_input_delay Board delay from fpga_dclk pin

of the CPLD to DCLK pin of the

FPGA

Simulating PFL Design

You can simulate the behavior of the PFL IP core with the ModelSim

-Altera software as it configures an

FPGA. This section provides guidelines on the PFL simulation for FPGA configuration.

Note:

PFL simulation is based on functional netlist, and does not support gate-level simulation. PFL

simulation does not reflect the true behavior of the hardware. Altera certifies the PFL IP core based

on actual hardware testing, and not through PFL simulation. The PFL simulation only provides

primitive behavioral simulation.

Table 8: Files Required for PFL Simulation in the ModelSim-Altera Software

File/Library Description

.vo or .vho The Verilog HDL or VHDL output file of the PFL IP core.

.sdo The Standard Delay Format Output file (.sdo) of the PFL IP core.

Simulation libraries:

• altera

• altera_mf

• maxii

• maxv

The precompiled library files for Altera IP core primitives and Altera CPLDs

in the ModelSim-Altera software.

Test bench Test bench file to establish the interface between the PFL IP core and the flash

memory device.

Flash simulation model

files

The simulation model files for the flash memory devices in the PS or FPP

configuration. For the flash simulation model file for each flash memory

device, refer to the respective flash memory device manufacturer.

UG-01082

2015.01.23

Simulating PFL Design

Parallel Flash Loader IP Core User Guide

Altera Corporation

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