Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Manual de usuario descargar pdf (Pagina 385)

100

101

Mentor Verification IP AE AXI4-Lite User Guide, V10.3

385

April 2014

Appendix B

SystemVerilog Test Programs

SystemVerilog AXI4-Lite Master BFM Test

Program

The following code example contains a simple master test program that shows the master BFM

API being used to communicate with a slave and create stimulus. This test program is discussed

further in “SystemVerilog Tutorials” on page 115.

// **********************************************************************

// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS

// THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS

// SUBJECT TO LICENSE TERMS.

// **********************************************************************

This is a simple example of an AXI4 master to demonstrate the

mgc_axi4_master BFM configured as axi4lite usage.

This master performs a directed test, initiating 4 sequential writes,

followed by 4 sequential reads. It then verifies that the data read out

matches the data written.

import mgc_axi4_pkg::*;

module master_test_program #(int AXI4_ADDRESS_WIDTH = 32, int

AXI4_RDATA_WIDTH = 1024, int AXI4_WDATA_WIDTH = 1024)

(

mgc_axi4_master bfm

);

// Enum type for master ready delay mode

// AXI4_VALID2READY - Ready delay for a phase will be applied from

// start of phase (Means from when VALID is asserted).

// AXI4_TRANS2READY - Ready delay will be applied from the end of

// previous phase. This might result in ready before

valid.

typedef enum bit

{

AXI4_VALID2READY = 1'b0,

AXI4_TRANS2READY = 1'b1

} axi4_master_ready_delay_mode_e;

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