Altera Interlaken MegaCore Function Manual de usuario Pagina 41
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Chapter 4: Functional Description 4–15
Transmit Path
June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
Figure 4–9 shows non-optimal utilization of the Interlaken link. In this case, the
application deasserts its valid signal when it does not have data ready to transfer. As a
result of this gap in incoming data, the Interlaken MegaCore function inserts Idle
symbols on the Interlaken link. In this example, multiple Idle symbols are inserted as
a result of the three cycles in which the application holds the valid signal low.
Figure 4–10 shows the end of the 1016-byte packet transfer, and the beginning of a
new packet transfer. Because the 1016-byte packet transfer uses only 64 bits of the
final 128-bit application data word on the channel, the
tx_ch0_datain_empty
signal
has value eight to indicate that the least significant eight bytes in this word are
invalid. Only the eight most significant bytes hold valid data.
Figure 4–9. Non-optimal Link Utilization Caused During 1016-Byte Packet Transfer on Channel 0
tx_mac_c_clk
tx_ch0_datain_ready
tx_ch0_datain_valid
tx_ch0_datain_data[127:0]
tx_ch0_datain_empty[3:0]
tx_ch0_datain_startofpacket
tx_ch0_datain_endofpacket
tx_ch0_datain_error
4h'0 4h'0 4h'0 4h'0 4h'0 4h'0 4h'0
12 3
Figure 4–10. End of 1016-Byte Packet Transfer and Beginning of New Packet Transfer on Channel 0
tx_mac_c_clk
tx_ch0_datain_ready
tx_ch0_datain_valid
tx_ch0_datain_data[127:0]
tx_ch0_datain_empty[3:0]
tx_ch0_datain_startofpacket
tx_ch0_datain_endofpacket
tx_ch0_datain_error
B1008-
B1016
B992-
B1007
B0-B15
B16-B31
4h'0 4h'0 4h'0 4h'0 4h'8 4h'0 4h'0 4h'0 4h'0 4h'0
- User Guide 1
- Interlaken MegaCore Function 1
- Contents 3
- Chapter 5. Signals 4
- Contents v 5
- Features 7
- Device Family Support 8
- MegaCore Verification 9
- Release Information 10
- Installation and Licensing 10
- OpenCore Evaluation 12
- 2. Getting Started 13
- Qsys Design Flow Summary 14
- Qsys Design Flow 16
- Specifying Parameters 17
- Completing the Qsys System 18
- Simulating the System 18
- Specifying Constraints 19
- I/O Standard Constraints 20
- 3. Parameter Settings 23
- Lane Rate 24
- Number of Words in Meta Frame 24
- Exclude Transceiver 24
- Burst Parameters 25
- 4. Functional Description 27
- Architecture Overview 28
- Interfaces Overview 28
- Note to Table 4–1: 29
- Avalon-ST Interface 30
- Clocking and Reset Structure 31
- MAC Clock Verified Frequency 35
- PCS Clock Frequencies 36
- Transmit Path 37
- Receive Path 43
- Channel Filtering Blocks 45
- Packet Regrouper 45
- Calendar and Status Block 46
- Lane Status Block 47
- High-Speed I/O Block 48
- Transceivers 49
- 5. Signals 53
- Exclude transceivers 54
- Chapter 5: Signals 5–3 55
- Note to Table 5–2: 56
- Note to Table 5–3: 56
- Application Interface Signals 57
- Note to Table 5–6: 58
- Chapter 5: Signals 5–7 59
- Note to Table 5–8: 60
- Note to Table 5–9: 61
- Note to Table 5–10: 61
- Note to Table 5–11: 62
- Note to Table 5–12: 62
- Transceiver Banks 63
- Running a Design Example 65
- Setting Up the Design Example 66
- Function 69
- Simulation 73
- Reset Signals 79
- Required Reset Sequence 80
- Additional Information 87
- Typographic Conventions 88
- Visual Cue Meaning 89
- Info–4 Additional Information 90
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