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Chapter 3: Specifications 3–21
HyperTransport MegaCore Function Specification
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
Figure 3–12 shows a 32-byte write interrupted with user-inserted wait states the clock
cycle after the command Sop_o = 1 is asserted.
Figure 3–13 shows a 38-byte read response, target done, and 16-byte read response
transferred back to back across the Rx interface with no delays.
Figure 3–12. 32-Byte Write with User-Inserted Wait States across Rx Interface Timing Diagram
Notes to Figure 3–12:
(1) Dav_o is shown to deassert initially, indicating that the Rx buffer does not have any additional packets stored beyond the one that is currently
being read.
(2) The user-side logic deasserts Ena_i to insert a wait state (for example to decode a command).
(3) Ena_i is low at this time so that the next command (indicated by Dav_o) is held off.
(4) Outputs are still valid, the user must qualify them with the previous Ena_i to determine if it is new data.
(5) BarHit_o is valid while Val_o and Sop_o are asserted.
234567 910
RefClk
Dav_o
81
Ena_i
Dat_o[31:0]
Dat_o[63:32]
Val_o
Sop_o
Eop_o
Mty_o[2:0]
11
DW0 DW2 DW4 DW6
DW1 DW3 DW6 DW7
0b000
Addr[39:8]
(4)
Write
(4)
(2) (3)
(4)
(4)
BarHit_o[2:0]
Matching Bar (4)
(1)
Figure 3–13. Streaming Responses Transferred across Rx Interface Timing Diagram
Notes to Figure 3–13:
(1) Dat_o[63:32] is not valid during this time because the command is only a 4-byte read response.
(2) Dat_o[63:32] is not valid during this time because the response is only seven double words long.
(3) Dat_o[63:32] is not valid during this time because the command is only a 4-byte target done.
234567 910
RefClk
Dav_o
81
Ena_i
Dat_o[31:0]
Dat_o[63:32]
Val_o
Sop_o
Eop_o
Mty_o[2:0]
11
RdResp DW0 DW2 DW4 DW6
DW1 DW3 DW5
(1) (2)
0b000 0b100
(1)(3)
TgtDone RdResp DWa
DWb
DWc
DWd
0b000
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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