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2–8 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide
Running the Clock Uncertainty Calculator Flow
Using the Advanced Clock Uncertainty Calculator
The third worksheet contains the advanced clock uncertianty calculator.
From Step 1. Enter PLL Information, as shown in Figure 2–8, enter the
PLL indices for source clock and destination clock before you click the
green Step 2. Calculate Clock Uncertainty Values button.
Under the Source Clock and Destination Clock cells in Figure 2–8, there
are first PLL and second PLL cells on the worksheet, which means the
advanced clock uncertianty calculator supports designs with cascaded
PLLs and each clock path has a maximum of two PLLs cascaded.
If there is no PLL in the design, you still must enter "0" for the first PLL
cell on the worksheet.
As in the advanced clock uncertianty calculator, click the yellow Reset
Ta ble button to clear all previous clock uncertainty results. You can enter
notes for reference in the last cell of the table. The advanced clock
uncertianty calculator supports up to 200 clock transfer combinations.
Figure 2–8. HardCopy II Advanced Clock Uncertainty Calculator without Calculation
Before beginning the calculation of clock uncertainty values, refer to the
clock transfer report and PLL_Names.txt. The clock transfer report shows
all clock-to-clock transfers in detail and PLL_Names.txt provides the
corresponding PLL index for each PLL name. Figure 2–9 show how to
enter the PLL indices for the advanced clock uncertianty calculator:
1st PLL 2nd PLL 1st PLL 2nd PLL Setup (ps) Hold (ps) Setup (ps) Hold (ps) Setup (ps) Hold (ps)
1
2
3
4
5
Enter User's Notes
(Optional)
Step 3. Read Clock Uncertainty Values
MessagesTransfer
Source Clock Destination Clock Intra-clock Inter-Clock IO Transfer
Step 1. Enter PLL Information
Step 2. Calculate Clock
Uncertainty Values
Step 2. Calculate Clock
Uncertainty Values
Reset Table
Res et Tabl e
- User Guide 1
- UG-01015-1.0 2
- Contents 3
- About this User Guide 5
- Typographic 6
- Conventions 6
- Chapter 1. About HardCopy II 7
- General 8
- Description 8
- PLL Extraction 9
- Clock Transfer Report 10
- Intra-Clock Transfer 11
- Inter-Clock Transfer 11
- I/O Transfer 12
- Instructions 12
- Clock Uncertainty Calculator 13
- 1–8 Altera Corporation 14
- General Description 14
- Chapter 2. Launching the 15
- HardCopy II Clock 15
- Uncertainty Calculator 15
- System and 16
- Software 16
- Requirements 16
- Running the 17
- Uncertainty 17
- Calculator Flow 17
- 2–4 Altera Corporation 18
- Altera Corporation 2–5 19
- 2–6 Altera Corporation 20
- Altera Corporation 2–7 21
- 2–8 Altera Corporation 22
- Altera Corporation 2–9 23
- 2–10 Altera Corporation 24
- Altera Corporation 2–11 25
- 2–12 Altera Corporation 26
- Chapter 3. Design Case 27
- Exceptions 27
- Various Clock 28
- Structures 28
- Clock Divider 29
- Ripple Clock 29
- Multiple Clock Networks 30
- Multi-Cycle Clock 30
- Altera Corporation 3–5 31
- Design Case Exceptions 31
- Clock Transfer Type 32
- Setup CU (ps) Hold CU (ps) 32
- Intra-Clock 32
- Inter-Clock 32
- I/O Interface 32
- Appendix A. Clock Transfer 33
- Examples 33
- A–2 Altera Corporation 34
- Intra-Clock Domain with PLL 34
- 11 — 11 — 34
- Domain without 35
- Domain with 36
- Altera Corporation A–5 37
- A–6 Altera Corporation 38
- Inter-Clock Domain with PLL 38
- Altera Corporation A–7 39
- A–8 Altera Corporation 40
- 12 — 0 — 40
- Altera Corporation A–9 41
- Altera Corporation A–13 45
- Cascaded PLLs 46
- Altera Corporation A–15 47
- Altera Corporation A–17 49
- A–18 Altera Corporation 50
- Altera Corporation A–19 51
- A–20 Altera Corporation 52
- Altera Corporation A–21 53
- A–22 Altera Corporation 54
- 12 3 12 7 54
- Altera Corporation A–23 55
- A–24 Altera Corporation 56
- 0 — 10 11 56
- Altera Corporation A–25 57
- 12 2 0 — 57
- A–26 Altera Corporation 58
- 10 — 4 8 58
- Altera Corporation A–27 59
- A–28 Altera Corporation 60
- A–30 Altera Corporation 62
- 10 2 0 — 62
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