Altera Device-Specific Power Delivery Network Manual de usuario descargar pdf (Pagina 25)

Chapter 1: User Guide for the Device-Specific Power Delivery Network (PDN) Tool 1–21

Design PCB Decoupling Using the PDN Tool

September 2012 Altera Corporation Device-Specific Power Delivery Network (PDN) Tool User Guide

In Step 3, you need to have a good estimate of the parameters entered to derive the

proper decoupling guidelines (Z

TARGET

and F

EFFECTIVE

). Although you need to

determine those guidelines based on the worst-case scenario, pessimistic settings

result in hard-to-achieve guidelines and over design of your PCB decoupling. For the

recommended settings of the percentage of transient current and maximum allowable

voltage ripple for selected power rail, refer to Table 1–1 on page 1–4.

In Step 4, you must adjust the number and value of the PCB capacitors in the

Decoupling Capacitor (Mid/High Frequency) and Decoupling Capacitor (Bulk)

fields to keep the plotted Z

EFF

below Z

TARGET

until F

EFFECTIVE

. If you are not able to

find a capacitor combination that meets your design goal, you can try to change the

parameters at Step 2; for example, reducing the BGA via inductance used in the

Calculate option by reducing the BGA via length in the BGA_VIA tab and using the

low option for plane spreading. These changes reduce parasitic inductance and make

it easier to achieve your decoupling goal. To achieve the low spreading setting, you

must place the mid to high frequency PCB capacitors close to the FPGA device. You

also must minimize the dielectric thickness between the power and ground plane.

If you are not able to meet the Z

TARGET

requirement with the above changes, the PDN

in your design may have reached its physical limitation under the parameters entered

in Step 3. You need to go back to Step 3 and re-examine these parameters to check if

they are over pessimistic.

The design shown in Figure 1–16 is a decoupling example for S4GX230KF40 VCC

power rail. Assume that the minimum voltage supply is 0.9 V, I

MAX

is 7 A, transient

current is 50% of I

MAX

, and the maximum allowable ripple is 3% of supply voltage.

The V

rail has 50 power BGA vias. The length of BGA via is assumed to be 60 mil.

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