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Signal Direction Description
rx_st_be[<n>-1:0] Output Byte enables corresponding to the rx_st_data. The byte enable
signals only apply to PCI Express Memory Write and I/O Write
TLP payload fields. When using 64-bit Avalon-ST bus, the width
of rx_st_be is 8 bits. When using 128-bit Avalon-ST bus, the
width of rx_st_be is 16 bits. This signal is optional. You can
derive the same information by decoding the FBE and LBE fields
in the TLP header. The byte enable bits correspond to data bytes
as follows:
• rx_st_data[127:120] = rx_st_be[15]
• rx_st_data[119:112] = rx_st_be[14]
• rx_st_data[111:104] = rx_st_be[13]
• rx_st_data[95:88] = rx_st_be[12]
• rx_st_data[87:80] = rx_st_be[11]
• rx_st_data[79:72] = rx_st_be[10]
• rx_st_data[71:64] = rx_st_be[9]
• rx_st_data[7:0] = rx_st_be[8]
• rx_st_data[63:56] = rx_st_be[7]
• rx_st_data[55:48] = rx_st_be[6]
• rx_st_data[47:40] = rx_st_be[5]
• rx_st_data[39:32] = rx_st_be[4]
• rx_st_data[31:24] = rx_st_be[3]
• rx_st_data[23:16] = rx_st_be[2]
• rx_st_data[15:8] = rx_st_be[1]
• rx_st_data[7:0] = rx_st_be[0]
This signal is deprecated.
rx_st_parity[<n>-1:0]
Output
The IP core generates byte parity when you turn on Enable byte
parity ports on Avalon-ST interface on the System Settings tab
of the parameter editor. Each bit represents odd parity of the
associated byte of the rx_st_datarx_st_data bus. For example,
bit[0] corresponds to rx_st_data[7:0] rx_st_data[7:0], bit[1]
corresponds to rx_st_data[15:8].
For more information about the Avalon-ST protocol, refer to the Avalon Interface Specifications.
Related Information
Avalon Interface Specifications.
Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface
To facilitate the interface to 64-bit memories, the Arria 10 Hard IP for PCI Express aligns data to the
qword or 64 bits by default. Consequently, if the header presents an address that is not qword aligned, the
Hard IP block shifts the data within the qword to achieve the correct alignment.
6-6
Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface
UG-01145_avst
2015.05.04
Altera Corporation
Interfaces and Signal Descriptions
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- Solutions 1
- Contents 2
- Datasheet 8
- Arria 10 Features 9
- Interface 10
- UG-01145_avst 11
- 2015.05.04 11
- Release Information 13
- Device Family Support 14
- Configurations 14
- Altera FPGA 15
- Debug Features 17
- IP Core Verification 18
- Recommended Speed Grades 18
- Qsys Design Flow 21
- Generating the Testbench 22
- Simulating the Example Design 22
- Directory Description 23
- Time TLP Type Payload 23
- TLP Header 23
- Modifying the Example Design 26
- Component 27
- File Name Description 28
- Subscribe 31
- 2014.08.18 32
- Generating the Qsys System 33
- Parameter Value 34
- Parameter Settings 44
- Parameter Value Description 45
- Device Capabilities 52
- Error Reporting 53
- Link Capabilities 54
- MSI and MSI-X Capabilities 55
- Slot Capabilities 56
- Power Management 57
- PHY Characteristics 58
- Avalon‑ST RX Interface 68
- Packet TLP 73
- Aligned Addresses 77
- Avalon-ST TX Interface 82
- Single Packet Per Cycle 95
- Data 0 Header 2 96
- Clock Signals 97
- Signal Direction Description 100
- Related Information 101
- ECRC Forwarding 102
- Error Signals 102
- Interrupts for Endpoints 103
- Interrupts for Root Ports 104
- Completion Side Band Signals 104
- Signal Directi 105
- Description 105
- Parity Signals 107
- LMI Signals 108
- Altera Corporation 112
- Send Feedback 112
- D E F 0 1 2 3 113
- Field and Bit Map 117
- 0134678951 117
- Bit(s) Field Description 118
- Power Management Signals 120
- 15 011623 8 2791213142431 121
- Bits Field Description 122
- Serial Data Signals 123
- PIPE Interface Signals 123
- Test Signals 128
- Registers 129
- Altera-Defined VSEC Registers 136
- CvP Registers 137
- Bits Register Description 141
- Arria 10 Reset and Clocks 144
- Clock Domains 147
- Clock Summary 149
- Interrupts 150
- MSI Interrupts 151
- Allocated 152
- Implementing MSI-X Interrupts 153
- Legacy Interrupts 155
- Error Handling 157
- Physical Layer Errors 158
- Data Link Layer Errors 158
- Transaction Layer Errors 159
- Error Type Description 160
- Status Bit Conditions 163
- IP Core Architecture 165
- Hard IP for PCI Express 166
- Top-Level Interfaces 167
- Clocks and Reset 168
- Hard IP Reconfiguration 168
- Transaction Layer 169
- Configuration Space 170
- (Soft Logic) 172
- Data Link Layer 174
- Physical Layer 176
- TX Packets 177
- Supported Message Types 179
- Power Management Messages 180
- Error Signaling Messages 181
- Locked Transaction Message 182
- Slot Power Limit Message 182
- Vendor-Defined Messages 182
- Hot Plug Messages 183
- Receive Buffer Reordering 185
- Using Relaxed Ordering 187
- Throughput Optimization 190
- Throughput of Posted Writes 192
- Design Implementation 194
- SDC Timing Constraints 195
- Optional Features 196
- ECRC on the RX Path 197
- ECRC on the TX Path 198
- TLP on Applica‐ 199
- TLP on Link Comments 199
- Testbench and Design Example 201
- Root Port Testbench 203
- Chaining DMA Design Examples 204
- Root Complex 205
- Chaining DMA 205
- Hard IP for 205
- PCI Express 205
- BAR/Address Map 208
- Memory BAR Mapping 209
- Bit Field Description 210
- Addr Register Name 211
- Byte Address 213
- Offset to Base 213
- Descriptor Type Description 213
- Test Driver Module 215
- DMA Write Cycles 216
- DMA Read Cycles 218
- Root Port Design Example 220
- Root Port 221
- Variation 221
- (variation_name.v) 221
- Root Port BFM 222
- BFM Configuration Procedures 223
- BFM Request Interface 223
- BFM Memory Map 224
- Offset (Bytes) Description 226
- BFM Procedures and Functions 230
- Location altpcietb_bfm_rdwr.v 231
- Shared Memory Constants 239
- Constant Description 240
- Location 245
- Setting Up Simulation 257
- Debugging 259
- Use Third-Party PCIe Analyzer 263
- BIOS Enumeration Issues 263
- Frequently Asked Questions 264
- 7 6 5 4 3 2 1 0 265
- Core Config 8 4 1 265
- Additional Information 267
- Date Version Changes Made 268
- How to Contact Altera 272
- Typographic Conventions 273
- Visual Cue Meaning 274
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