Altera JNEye Manual de usuario

JNEye User GuideSubscribeSend FeedbackUG-11462015.05.04101 Innovation DriveSan Jose, CA 95134www.altera.com

Figure 2-4: JNEye Channel WizardThe Channel Wizard displays the channel characteristics and allows you to verify the correctness of thechannel compone

Figure 2-76: Rise/fall Time Histogram PlotWaveformFor Hybrid mode or Full Waveform mode simulations, a waveform of each test point is plotted. The Dat

Simulation ReportA simulation report is shown in the last page of the output windows. The simulation report is organizedas follows:• Simulation Log—If

PLL Type: Enable PLL Bandwidth: SVGX_TXPLL_High TX Pre-emphasis/FIR Mode: Off Jitter & Noise Configur

Vod=H (Auto Mode, Method = Area) Eye Width=0.41UI (39.867ps), Eye Height= 182.92mV, Jitter(p-p)=0.59UI (57.102ps) Random Jitter=

simulations. JNEye simulation output data is usually located in a file directory that has the same name asthe saved project name. For example, if the

Figure 2-78: Start JNEye Channel Viewer from JNEye Controller ModuleThere are four ways to start JNEye Channel Viewer:• Double-click the JNEye_Channel

Figure 2-79: JNEye Channel Viewer User InterfaceThe following figure shows the Channel Viewer GUI panel partitions.2-100JNEye Channel Viewer ModuleUG-

Figure 2-80: JNEye Channel Viewer GUI Panel PartitionsChannel Plot PanelThis panel contains the Channel Viewer and Plot Selector. The JNEye Channel Vi

Channel List PanelThis panel maintains the channels of interest. Channels can be either transferred from the JNEye ControlModule or added within the C

Figure 2-83: S-parameter with Port Configuration—Type 3Figure 2-84: S-parameter with Custom Port Configuration• Lane ID (Lane)—For multiple channel/la

Passivity Violation CheckResultsImpact on Link SimulationAccuracyRecommendationsSlight Passivity Violation There may not be a noticeableeffect in the

The Channel List Panel contains the following command buttons:• Add Channel—Open a file browser and locate the required channel model files.• Delete—D

S-parameter Mode PanelFigure 2-85: S-parameter Mode Panel• Mixed-Mode Selector Panel—This panel allows you to select and plot an S-parameter’s mixed-m

Plot Configuration PanelThe Channel Analysis and Compliance Module menu controls the channel characteristics plottingmodes:• Off—Channel Viewer plots

User-Directed Channel PlottingFigure 2-86: Plot Configuration Panel (Frequency Response)UG-11462015.05.04Plot Configuration Panel2-107Functional Descr

Figure 2-87: Plot Configuration Panel (Impulse Response and Single Bit Response)This panel allows you to select and configure the channel plotting. Th

Figure 2-88: Typical Frequency Domain Channel Characteristics PlotsThe JNEye Channel Viewer plots the channels’ amplitude and group delay frequency re

Figure 2-89: Combined Channel Response ExampleThe JNEye Channel Viewer can also plot channel responses in a time-domain. It can compute the impulseres

Figure 2-90: Impulse Response and Single-Bit Response ExamplesCombined time-domain channel responses can also be done in the JNEye Channel Viewer. The

Figure 2-92: Time-Domain Channel Plots with "Remove Propogation Delay" OptionChannel AnalysisThe following figure shows the Channel Analysis

Figure 2-93: Channel Analysis User InterfaceIn the Channel Analysis Configuration panel, the following parameters can be configured to your linkconfig

Link and Simulation SettingThe Link and Simulation Setting tab sets the global link parameters and simulation configurations.Figure 2-5: Link and Simu

• FEXT Tr/Tf—Far-end crosstalk aggressor 20%-80% rise/fall time• Crosstalk dB Factor—This parameter, Y, defines how dB is calculated where dB = Y*log1

Figure 2-94: Channel Analysis Module’s Insertion Loss Deviation (ILD) Analysis Example• Return Loss Plot—This plot is labeled CP: RL. In this plot, th

Figure 2-95: Channel Analysis Module’s Return Loss (RL) Analysis Example• Insertion Loss to Crosstalk Ratio Plot—This plot is labeled CP: ICR. In this

Figure 2-96: Channel Analysis Module’s Insertion Loss to Crosstalk Ratio (ICR) Analysis Example• Crosstalk Limit Plot—This plot is labeled CP: XTLK Li

Figure 2-97: Channel Analysis Module’s Crosstalk Limit Analysis Example10GBASE-KR Channel ComplianceThe following figure shows the 10GBASE-KR channel

Figure 2-98: 10GBASE-KR Channel Compliance Check User InterfaceAll parameters are predefined as described in the IEEE 802.3ap/10GBASE-KR standards, so

Figure 2-99: 10GBASE-KR Channel Compliance Module’s Insertion Loss Deviation (ILD) AnalysisExample• Return Loss Plot—This plot is labeled CP: RL. In t

Figure 2-100: 10GBASE-KR Channel Compliance Module’s Return Loss (RL) Analysis Example• Insertion Loss to Crosstalk Ratio Plot—This plot is labeled CP

Figure 2-101: 10GBASE-KR Channel Compliance Module’s Insertion Loss to Crosstalk Ratio (ICR)Analysis ExampleOIF CEI-28G-SR 3.0 and OIF CEI-25G-LR Chan

Figure 2-102: OIF CEI-28G-SR 3.0 Channel Compliance Check User InterfaceOIF CEI-25G-LR, OIF CEI-28G-MR, and OIF-CEI-28G-SR channel compliances are sim

Test PatternAllows you to specify the test pattern used in the simulation. The following test patterns are available:• PRBS-7, PRBS-9, PRBS-11, PRBS-1

Figure 2-103: OIF CEI-28G_SR 3.0 Channel Compliance Module’s Insertion Loss Deviation (ILD) AnalysisExample• Return Loss Plot—This plot is labeled CP:

Figure 2-104: OIF CEI-28G-SR 3.0 Channel Compliance Module’s Return Loss (RL) Analysis Example• Insertion Loss to Crosstalk Ratio Plot—This plot is la

Figure 2-105: OIF CEI-28G-SR 3.0 Channel Compliance Module’s Insertion Loss to Crosstalk Ratio (ICR)Analysis Example• Crosstalk Limit Plot—This plot i

Figure 2-106: OIF CEI-28G-SR 3.0 Channel Analysis Module’s Crosstalk Limit Analysis ExampleUG-11462015.05.04Plot Configuration Panel2-127Functional De

Options PanelFigure 2-107: Options PanelUse this panel to select the following plot options:• Enable Instant Plot—Enable and disable instant channel p

Output Options PanelTo generate images of new channel plots, click Save current plot to a file when the Output Image Typemenu is set to PNG, JPG, or G

Figure 2-109: JNEye Batch Simulation ControllerThe JNEye Batch Simulation Controller accepts JNEye simulation configuration (.jne) files. You can setu

• View Select Sim Result—Open and load simulation result (if available) of the selected job• Move Up (/\)—Move the highlighted job forward in the job

• Ideal transmission line• Via model based on composite transmission line blocks• Shunt and series capacitance• Series inductance• S-parameter modelA

Figure 2-110: JNEye Channel Designer User InterfaceUG-11462015.05.04JNEye Channel Designer2-133Functional DescriptionAltera CorporationSend Feedback

• Pattern Designer—Allows you to specify your own custom test patterns. The following figure showsthe Pattern Designer user interface.Figure 2-6: JNEy

• Connect—Use the straight line or right-angled line to connect channel components• Edit—User can use these commands to delete, copy, or paste channel

Channel ComponentsThe Channel Designer contains the following components:• Port 1—Port 1 is the input port of the channel under construction.• Port 2—

Figure 2-112: Capacitance and Inductance Channel Component Configuration in Channel WizardStripline ComponentA stripline uses a flat strip of metal th

relative permittivity of the substrate determine the characteristic impedance of the strip which is atransmission line. A typical stripline structure

After entering the model parameters, click Analyze and Channel Designer will compute the frequencyresponse of the current design. The integrated plott

Figure 2-114: Microstrip Channel Component ConfigurationThe channel component designer GUI can perform parameter unit conversion interactively. For ex

Coax ComponentA coax transmission line consists of two round conductors in which one completely surrounds the other.The two conductors are separated b

After entering the model parameters, click Analyze and Channel Designer will compute the frequencyresponse of the current design. The integrated plott

Figure 2-116: RLGC Transmission Line Channel Component ConfigurationThe channel component designer GUI can perform parameter unit conversion interacti

Figure 2-117: Ideal Transmission Line Channel Component ConfigurationThe channel component designer GUI can perform parameter unit conversion interact

• Custom—Click the open-file dialog button to select a custom test pattern file.Figure 2-7: Custom Test Pattern File Browser ButtonThe custom pattern

and the analytical via model structure is shown in the figure after that. The via is configured with thefollowing parameters:• Input parameters• Via•

Figure 2-119: PCB Via Analytical Model StructureThe channel component designer GUI can perform parameter unit conversion interactively. For example,yo

Tutorial: PCI Express 8GT32015.05.04UG-1146SubscribeSend FeedbackThis tutorial uses JNEye to run a link simulation. This example and its associated ch

Stratix V GX transmitter has a 4-tap FIR to compensate for channel effects. The PCI Express 8G receiverhas CTLE and a 1-Tap DFE per PCI-SIG definition

The ~18-inch backplane channel is described by a 12-port S-parameter model. The S-parameter ismeasured (or generated) with port configuration type 2,

Figure 3-3: Channel Characteristics (Using JNEye Channel Viewer with Data Cursor Enabled)The JNEye Channel Viewer shows that the backplane channel has

Phase Noise SpursFrequency Phase Noise (dBc) Frequency Amplitude (dBc)1 KHz –84 10 MHz –961 MHz and above –140Figure 3-4: Transmitter Reference Clock

Use the JNEye’s link optimization algorithm to find the optimal equalization settings for both thetransmitter and receiver. In this demonstration, you

• Simulation Mode: Hybrid• Output Options: Data Viewer with Image Output. This option tells JNEye to generate image files(.png) for all output plots.•

Transmitter TabFigure 3-7: Transmitter SettingsSet the following parameters in the Transmitter tab:• Transmitter: Stratix V GX• Package: Stratix V GX•

The reference clock frequencies listed are commonly used in most serial link protocols. If you cannot findthe exact reference clock frequency from the

Receiver TabFigure 3-8: Receiver SettingsSet the following parameters in the Receiver tab:• Receiver: PCI-Express 8GT• Package: PCI-Express 8GT• CTLE

Figure 3-9: Additional Receiver ConfigurationRelated InformationLink and Simulation Setting on page 2-6The Link and Simulation Setting tab sets the gl

channel and the crosstalk noises are superimposed. This section describes how to set up crosstalksimulation in JNEye.The backplane model is provided a

Perform the following steps to add the first crosstalk channel:1. Click Channel in the Link Designer panel and select Far-end Crosstalk (FEXT).2. Use

5. Set the aggressor frequency offset to 300 ppm to emulate the phase shifting effect for this crosstalknoise source. This setting indicates the 2nd c

Figure 3-13: Complete Link Connection in Link DesignerThe link configuration is complete. Use the Save/Save as buttons to save the configuration for l

Figure 3-14: Channel Characteristics of Victim and 2 FEXT Channels (with Data Cursor Enabled)Start the channel simulation by clicking Simulate in the

• The first figure is a hybrid eye diagram that includes deterministic jitter and probability densityfunction (PDF) because of unbounded jitter and no

Figure 3-16: Transmitter Output TIE (Time Interval Error) Plots with Reference Clock Phase Noise andSpurs Before and After the Golden CDRIn the follow

When you enable a PLL in a transmitter, the reference clock’s phase noise is shaped and filtered with thePLL’s response. The following figure shows th

• Option 1: Reference Clock JitterFigure 2-9: Reference Clock Option 1: Reference Clock JitterUG-11462015.05.04Link and Simulation Setting2-11Function

Figure 3-19: Channel Output Hybrid Eye Diagrams and BER AnalysisThe CTLE is a PCI-Express 8GT CTLE behavior model output stage. The JNEye's link

Figure 3-20: CTLE Output Hybrid Eye Diagram and BER Analysis with Ideal Clock3-20AnalysisUG-11462015.05.04Altera CorporationTutorial: PCI Express 8GTS

Figure 3-21: CTLE Output Hybrid Eye Diagram and BER Analysis with CDR Recovered ClockWhen you enable CDR in a receiver, the reference clock’s phase no

Figure 3-22: Phase Noise of Reference Clock and Its Transitions through PLL and CDRAt the output of the PCI-Express 8G receiver’s 1-Tap DFE, the follo

Figure 3-23: TP4 Hybrid Eye Diagram and BER Analysis Measured with Ideal ClockThe PCI-Express 8GT eye diagram mask is shown in the following figure to

Figure 3-24: TP4 Hybrid Eye Diagram Measured with CDR Recovered Clock and PCI-Express 8GTReceiver Eye Diagram MaskWhen you enable a CDR in a receiver,

Figure 3-25: Phase Noise of Reference Clock and Its Transitions through PLL and CDRThese examples demonstrated how to use JNEye to set up a serial lin

Related InformationLink and Simulation Setting on page 2-6The Link and Simulation Setting tab sets the global link parameters and simulation configura

Tutorial: 28 Gbps OIF VSR Link with Arria 10 GT42015.05.04UG-1146SubscribeSend FeedbackThis tutorial uses JNEye to run an OIF VSR 28 Gbps link simulat

To accomplish these goals, set up a transmitter model, a receiver model, and a link with the followingparameters:• Data rate: 28 Gbps• Test pattern: P

Option 1 configures the reference clock with the following options:• Random Jitter— Specify the frequency range (in ps).Note: Altera recommends that t

Figure 4-2: OIF VSR Channel CharacteristicsThe JNEye Channel Viewer shows that the channel has approximately 7.4 dB loss at 14 GHz. The fourcrosstalk

Setting Up the Control ModuleLink and Simulation TabFigure 4-3: Link and Simulation SettingsSet the following parameters in the Link and Simulation Se

Transmitter TabFigure 4-4: Transmitter SettingsSet the following parameters in the Transmitter tab:• Transmitter: Arria 10 GT (use the Link Designer o

Receiver TabFigure 4-5: Receiver SettingsSet the following parameters in the Receiver tab:• Receiver: Arria 10 GT (use the Link Designer or Receiver t

Perform the following steps to add a victim channel:1. Click Channel in the Link Designer and select Transmission.2. Use the file browser to locate th

• Because the crosstalk channel is provided as a single-lane 4-port S-parameter, there is no differencebetween near-end (NEXT) and far-end (FEXT) cros

Completing the SystemAll the link components are now chosen and placed in the Link Designer. Click Connect in the LinkDesigner to begin connecting the

Figure 4-9: Channel Characteristics of Victim and 2 FEXT ChannelsStart the channel simulation by clicking Simulate in the lower right corner of the JN

• The first figure (top left) is a hybrid eye diagram that includes deterministic jitter and probabilitydensity function (PDF) because of unbounded ji

The following figure shows that the transmitter output jitter, which includes the transmitter output jitter,is about 0.33 UI at BER 10–15.Figure 4-11:

• Option 2: Phase NoiseFigure 2-10: Reference Clock Option 2: Phase NoiseUG-11462015.05.04Link and Simulation Setting2-13Functional DescriptionAltera

Figure 4-12: Channel Output Hybrid Eye Diagrams and BER AnalysisAt the CTLE output, the signal after the receiver’s CTLE, the Arria 10 GT CTLE AC gain

Figure 4-13: CTLE Output Hybrid Eye Diagram and BER Analysis with Ideal Clock4-14AnalysisUG-11462015.05.04Altera CorporationTutorial: 28 Gbps OIF VSR

Figure 4-14: CTLE Output Hybrid Eye Diagram and BER Analysis with CDR Recovered ClockThis example demonstrated how to use JNEye to set up an OIF VSR 2

Additional Information52015.05.04UG-1146SubscribeSend FeedbackAdditional information about the document and Altera.Document Revision HistoryDate Versi

How to Contact AlteraTable 5-1: Altera Contact InformationContact(3)Contact Method AddressTechnical support Website www.altera.com/supportTechnical tr

ContentsSystem Requirements and Installation Guide...1-1System Requirements...

Option 2 configures the reference clock with the following options:• Phase Noise—Specify reference clock jitter using a phase noise profile. Reference

• FIR => CTLE => DFE— (default) Optimizes the link performance by finding the optimal transmittersetting, receiver equalization setting, or both

the link represent the link margin at the specified bit error rate (BER) target. Link marginsimulation using transmitter and receiver jitter provides

Figure 2-12: Diamond-Shaped Eye Diagram Mask EditorA custom eye diagram mask can be saved and loaded for future use.Project NameA user-defined name fo

Table 2-5: Simulation ModesPDF = Probability Density FunctionStatistical Mode Full Waveform Mode Hybrid Mode (Default)Simulation Method Statistical Me

Test Point OptionsJNEye provides the following default test point options:• Data Latch Only—(default option) Simulation results at the data latch will

Figure 2-13: Jitter Component Supported in JNEye Jitter Analysis FeatureThe jitter decomposition process (conceptual) is shown in the following figure

Figure 2-14: Jitter Decomposition Process (Conceptual)In JNEye 15,0, the following jitter components are extracted and reported:• PJ—Periodic jitter (

Transmitter SettingThe transmitter generates signals based on the transmitter clock and test pattern conditions.Figure 2-15: JNEye Transmitter Setting

JNEye comes with the following transmitter package models:• Stratix V GX• Arria V GZ• Stratix V GT• Arria 10 GX/SXOptions: Additional package models (

Additional Information... 5-1Document Revision History...

Pre-EmphasisSelect or specify the transmitter pre-emphasis, de-emphasis, or TX-FIR configuration in one of thefollowing modes:• Auto—JNEye uses its li

Supply VoltageFor supported devices, you can choose the supply voltage. In JNEye 15.0, the Arria 10 GX/SX/GTtransmitter model provides the following s

Table 2-7: JNEye to Quartus II Parameter Translation for Arria 10 GX/SX/GT TransmittersJNEye Name Quartus II NameVod Selection Transmitter Output Swin

Figure 2-17: Transmitter Jitter DecompositionTable 2-8: Transmitter Intrinsic Jitter and Noise TypesName Description Unit Supportin JNEyeCommentsDJ De

Name Description Unit Supportin JNEyeCommentsDCD Duty CycleDistortionUI Yes The DCD parameter models two types of jitter:Positive pulse width jitter (

Name Description Unit Supportin JNEyeCommentsJitter PDF JitterProbabilityDensityFunction(PDF)Jitteramplitude,Probability(Jitteramplitude canbe in abso

• Jitter/Noise Component mode—JNEye uses a flat jitter/noise structure that assumes no overlappingamong all the jitter and noise components. Avoid dou

• DJ/RJ-DN/RJ mode—All deterministic jitter/noise components are included in DJ and DN.Figure 2-20: Specifying Transmitter Jitter and Noise in DJ/RJ-D

Note: Jitter specified in the Transmitter Noise/Jitter panel is the transmitter’s intrinsic jitter and noise.Jitter specified in the Reference Clock c

Pulse Shaping tabJNEye supports two pulse shaping methods for Custom transmitters:• Edge Rate—A pulse-shaping filter is generated by using a Gaussian

System Requirements and Installation Guide12015.05.04UG-1146SubscribeSend FeedbackJNEye is a high-speed transceiver link simulation. When you design h

Figure 2-24: Transmitter Options: Transmitter FIR, Pre-emphasis, and De-emphasis ConfigurationPLL tabUse this panel to set the custom PLL divider rati

Figure 2-25: Transmitter Options: PLL ConfigurationMisc tabReserved. This tab is blank.Characterization Data AccessCharacterization Data Access—Transm

Use the following guidelines for characterization data access:• When Stratix V GX, Stratix V GT, Arria V GZ, or Arria 10 GX/SX/GT is selected, the Cha

Figure 2-26: Characterization Data Access: PVT Conditions and Jitter/Noise Lock Check BoxFigure 2-27: Characterization Data Access Usage and MessageIB

• Package—Package models are required in all IBIS models. JNEye includes the IBIS package model inthe simulation by default. You can choose other pack

Figure 2-29: Transmitter IBIS-AMI Model AMI Configuration Tab• Model Name—IBIS-AMI model nameUG-11462015.05.04Characterization Data Access2-39Function

• Reserved Parameters:• The IBIS-AMI reserved parameters are shown. The reserved parameters are meant for the JNEyesimulation configuration.• IBIS-AMI

• Model Specific Parameters—This section lists all the model specific parameters that the IBIS-AMImodel provides. You can use their selections or spec

Figure 2-31: Transmitter IBIS-AMI Model Status TabConsider the following for the IBIS-AMI transmitter modeling support in JNEye:• JNEye only supports

JNEye provides the following settings and configurations for receivers:ReceiverThe following receiver types are supported:• Stratix V GX• Arria V GZ•

InstallationTo install JNEye, perform the following steps:1. Acquire the JNEye 15.0 Installation Package from the Altera Download Center.2. Execute th

JNEye comes with the following receiver package models:• Stratix V GX• Arria V GZ• Stratix V GT• Arria 10 GX/SXOptions: Additional package models (sho

• Altera device receivers:• Stratix V GX, Arria V GZ, Stratix V GT, Arria 10 GX/SX, and Arria 10 GT CTLE models areembedded in JNEye.• Both Auto and M

• Altera receivers:• Stratix V GX, Arria V GZ, Aria 10 GX/SX, and Arria 10 GT DFE models are supported in bothAuto mode and Manual mode.• In Auto mode

Table 2-10: Receiver PVT Model CoverageReceiver Type Waveform PVT Model Jitter/Noise PVT ModelStratix V GX Typical Process: Typical/Fast/Slow Voltage:

JNEye Name Quartus II NameCTLE Setting / ModeEq_bw_sel (Equalizer bandwidth Selection)If Receiver High Data Rate Mode Equalizer = 1• 0: JNEye CTLE Set

JNEye Name Quartus II NameDFE Tap 2 Receiver Decision Feedback Equalizer Fix Tap TwoCoefficientDFE Tap 3 Receiver Decision Feedback Equalizer Fix TapT

Name Description Unit Support inJNEyeCommentsBUJ BoundedUncorrelatedJitterUI Yes Same as receiver’s Deterministic Jitter. Thedefault method is Uniform

Name Description Unit Support inJNEyeCommentsNoisePDFNoiseProbabilityDensityFunctionNoiseamplitude,ProbabilityYes Noise PDF defines the noise probabil

Figure 2-34: JNEye Receiver Jitter/Noise Configuration WindowCharacterization Data AccessYou can retrieve the receiver jitter values from the built-in

Use the following guidelines for characterization data access:• When Stratix V GX, Stratix V GT, Arria V GZ, or Arria 10 GX/SX/GT is selected, the Cha

If you have problems running JNEye after installing the program, follow these instructions:• Check whether the Microsoft Visual C++ 2013 library is on

Figure 2-35: Characterization Data Access: PVT Conditions and Jitter/Noise Lock Check BoxFigure 2-36: Characterization Data Access Usage and MessageA

Figure 2-37: Altera Receivers Jitter Data Usage Message WindowReceiver OptionsReceiver options provide further configuration and setting options for r

• Termination tab—This section specifies receiver impedance.Figure 2-38: Receiver Termination ConfigurationFor selected Altera devices, use the RX Imp

• Equalization tab—For Arria 10 GX/SX/GT, Stratix V GX, and Arria V GZ devices, the DFE model isembedded in the JNEye and is not configurable. For Cus

Figure 2-40: Receiver IBIS-AMI Model IBIS Configuration Page• Package—Package models are required in all IBIS models. JNEye includes the IBIS package

• Use External Termination—A checked box indicates that an external termination is used in thesimulation. The external termination (single-ended) is s

• Model Name—IBIS-AMI model name• Reserved Parameters:• The IBIS-AMI reserved parameters are shown. The reserved parameters are meant for the JNEyesim

Figure 2-42: Receiver IBIS-AMI Parameter Type Designation for Link OptimizationJNEye 15.0 supports link optimization with IBIS-AMI receiver models. On

Figure 2-43: Receiver IBIS-AMI Model Status TabNote: Consider the following for the IBIS-AMI receiver modeling support in JNEye:• JNEye only supports

Figure 2-44: JNEye Channel Setting with Link Design and Channel ListAn S-parameter channel component such as a connector, cable, or backplane can be d

Functional Description22015.05.04UG-1146SubscribeSend FeedbackJNEye Control ModuleDouble-click the JNEye.exe icon to launch JNEye.Figure 2-1: JNEye Co

Figure 2-45: S-parameter with Port Configuration – Type 1Figure 2-46: S-parameter with Port Configuration – Type 2Figure 2-47: S-parameter with Port C

Figure 2-48: S-parameter with Custom Port ConfigurationIf the S-parameter file is not Type 1, Type 2, or Type 3, you can use the Custom option in the

Figure 2-49: Custom Port Configuration in Channel Wizard• Lane—This field lists the channel lane ID number. For channel lane S-parameters that are 8-p

A crosstalk aggressor has the following parameters:• Source—Each crosstalk aggressor can be of Inline, Transmitter, or Aggressor type.• With an inline

• Location—For multiple channel/lane S-parameters simulating crosstalk effects, you must specify theaggressor location. For example, the above figures

Figure 2-51: JNEye Channel Viewer ExampleRefer to the Tutorial: PCI Express 8GT chapter for step-by-step channel setup instructions.Automatic S-parame

Batch Channel Simulation ConfigurationJNEye provides a convenient way to set up batch channel simulations. Batch channel simulationgeneration can be a

Figure 2-54: Batch Simulation Channel Selection Window2. Click Add Channel to select channel files. A file browser helps you select the channel files

Figure 2-55: Example of Batch Channel Selections3. When channel selection is complete, click Generate Simulation Configuration to generate JNEyesimula

Launch JNEye Batch Simulation Controller to run the generated link simulations (refer to the JNEyeBatch Simulation Controller section for details). Th

Figure 2-2: JNEye Link Designer ModuleTable 2-1: Supported Transmitter, Channel, and Receiver ComponentsTransmitter (TX) Component Channel Component R

Figure 2-58: Aggressor Transmitter with Three Individual Aggressor TransmittersFollow the steps described in the previous section to set up a link wit

Figure 2-59: Setting Up the Crosstalk Aggressor for a Crosstalk ChannelJNEye supports up to eight individual crosstalk aggressor transmitters. However

Figure 2-60: Aggressor Transmitter Tab2-76Crosstalk Aggressor Transmitter SettingUG-11462015.05.04Altera CorporationFunctional DescriptionSend Feedbac

Within the Aggressor Transmitter tab, there are eight aggressor types associated with the aggressor typesin the Channel Wizard’s Signal Source menu. E

• System tabFigure 2-61: JNEye System Options Window: System Tab• Output Directory—Specify an output directory for the simulation results according to

• Simulation tabFigure 2-62: System Options Window: Simulation Tab• Default Eye Diagram Plot Length—This parameter controls the waveform length used t

JNEye Data Viewer ModuleThe JNEye Data Viewer displays simulation and analysis results. The Data Viewer can be started in thefollowing ways:• Automati

The following GUI capabilities are provided in the Data Viewer:• Zoom control• In an eye diagram plot—Click Zoom In or click and drag a rectangle box

Figure 2-65: Data Cursor Example for Waveform Plot• Legends—Plot legends are shown when plots are generated. Use the Page-Up, Page-Down, Home,and End

simulation results when no jitter or noise is present. JNEye automatically chooses the most suitable colormap based on the type or configuration of a

points can be manually placed into the link by clicking Test Point and connecting to the desired locationin the link.The following rules of link const

Figure 2-66: JNEye Data Viewer PDF Eye Diagram and PlotsCumulative Distribution Function (CDF) Eye DiagramThis scope shows the CDF eye diagram (with p

Figure 2-67: JNEye Scope CDF and PlotsBER ContourThe Data Viewer shows the BER contour and eye diagram opening width and height. The eye diagramcompli

Figure 2-68: JNEye Scope BER Contour and PlotsQ-Factor CurveA different view of the BER bathtub curve using Q-factor.2-86JNEye Data Viewer ModuleUG-11

Figure 2-69: JNEye Data Viewer Q-Factor Plot (Time Axis)UG-11462015.05.04JNEye Data Viewer Module2-87Functional DescriptionAltera CorporationSend Feed

Figure 2-70: JNEye Data Viewer Q-Factor Plot (Amplitude Axis)Transmitter Reference Clock Phase Noise Analysis and PlotsJNEye plots the phase noise pow

Figure 2-71: Transmitter Reference Phase Noise Analysis (At Transmitter Output)UG-11462015.05.04JNEye Data Viewer Module2-89Functional DescriptionAlte

Figure 2-72: Transmitter Reference Phase Noise Analysis (At Receiver Output)TX pre-emphasis, de-emphasis, or FIR coefficients are displayed with the t

Figure 2-73: Time Interval Error (TIE) Plot with Jitter Analysis ResultsTime Interval Error (TIE) Histogram PlotsThis plot shows the histogram of TIE

Figure 2-74: Time Interval Error (TIE) Histogram with Jitter Analysis ResultsWaveform Spectrum PlotsThe frequency spectrum of the waveform is plotted.

Figure 2-75: Waveform Spectrum PlotRise/Fall Time Histogram PlotsJNEye calculates the rise/fall time across the bit time boundary.Note:JNEye computes