2–4 Chapter 2: Getting Started

8B10B Encoder /Decoder Walkthrough

8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation

Set Up Simulation

An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model

file produced by the Quartus II software. The model allows for fast functional

simulation of IP using industry-standard VHDL and Verilog HDL simulators.

c You may only use these models for simulation purposes and expressly not for

synthesis or any other purposes. Using these models for synthesis creates a

nonfunctional design.

To generate an IP functional simulation model for your MegaCore function, follow

these steps:

1. Turn on Generate Simulation Model.

2. Click Next (or the Summary page) to display the summary page .

Generate Files

To generate the files, perform the following steps:

1. On the Summary page, turn on the files you want to generate.

1 A gray checkmark indicates a file that is automatically generated; a red

checkmark indicates an optional file.

2. To generate the specified files and close the MegaWizard Plug-in Manager, click

Finish.

1 The generation phase may take several minutes to complete.

3. After you review the generation report, click Exit to close the MegaWizard Plug-In

Manager.

1 The Quartus II IP File (.qip) is a file generated by the MegaWizard interface

or SOPC Builder that contains information about a generated IP core. You

are prompted to add this .qip file to the current Quartus II project at the

time of file generation. In most cases, the .qip file contains all of the

necessary assignments and information required to process the core or

system in the Quartus II compiler. Generally, a single .qip file is generated

for each MegaCore function and for each SOPC Builder system. However,

some more complex SOPC Builder components generate a separate .qip

file, so the system .qip file references the component .qip file.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 31 32

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